LC89058W-E Datasheet, PDF (37/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
11.3.2 GPIOS=1
• _{The figure below shows the relationship between GPIO0, GPIO1, GPIO2, GPIO3 which are input to the selector and}
the DIR block signal, and RMCK, RBCK, RLRCK, RDATA which are output from the selector and the control signal.
ADC
24 ^SDIN
DIR
XIN-MCK
XIN-BCK
XIN-LRCK
PLL-MCK
PLL-BCK
PLL-LRCK
PLL-DATA
XM
radio
44 ^GPIO0
45 ^GPIO1
46 ^GPIO2
47 ^GPIO3
Lock judgment
4
“EXTSEL”
4
4
4
4
“EMCKP”
“EDTMUT”
RMCK ₁₆
RBCK ₁₇
RLRCK ₂₀
RDATA ₂₁
Figure 11.1 Selector Configuration Diagram
Table 11.1 Selector I/O Signals
Input Pin or Input Signal
EXTSEL=1
PLL Lock State
EXTSEL=0
PLL Unlock State
Output pin
GPIO0 (pin 44)
PLL-MCK
XIN-MCK
RMCK (pin 16)
GPIO1 (pin 45)
PLL-BCK
XIN-BCK
RBCK (pin 17)
GPIO2 (pin 46)
PLL-LRCK
XIN-LRCK
RLRCK (pin 20)
GPIO3 (pin 47)
PLL-DATA
SDIN
RDATA (pin 21)
Note: The selector output generated when the PLL is locked can be changed to the XIN clock system by setting the
OCKSEL and RCSEL.
• _{EXTSEL is enabled by setting GPIOS=1. When GPIOS=0 is set, the state of EXTSEL=0 is output from each pin.}
• _{The clock input to GPIO0 can be inverted by EMCKP and sent to RMCK.}
• _{The data to be input to GPIO3 must conform to the PLL-DATA or SDIN audio format.}
• _{The data input to GPIO3 can be muted by EDTMUT.}
• _{EMCKP and EDTMUT are enabled when GPIOS=1 is set.}
• _{The above settings are valid only when the master mode is set and must not be set when the slave mode is set.}
No.A1056-37/64