LC89058W-E Datasheet, PDF (19/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
10 Description of Demodulation Function
10.1 Clocks
10.1.1 PLL (LPF)
• The LC89058W-E incorporates a VCO (Voltage Controlled Oscillator) that
can be stopped with PLLOPR and it synchronizes with sampling frequencies (fs)
from 32kHz to 192kHz and with the data with transfer rate from 4MHz to
25MHz. PLL is locked at 512fs.
• LPF is a pin for PLL loop filter. Connect the following resistance and capacitance
shown in the figure.
LPF
R0
C0
C1
R0 : 220Ω
C0 : 0.1μF
C1 : 0.022μF
Figure 10.1 Loop Filter Configuration
10.1.2 Oscillation amplifiers (XIN, XOUT, XMCK)
• The LC89058W-E features a built-in oscillation amplifier. Connecting a quartz resonator, feedback resistor, and load
capacitance to XIN and XOUT can configure an oscillation circuit. When connecting a quartz resonator, use one with
a fundamental wave. Be aware that the load capacitance depends on the quartz resonator characteristics.
• If the built-in oscillation amplifier is not used and oscillation module is used as the clock source instead, connect the
output of an external clock supply source to XIN. At this time, it is not necessary to connect a feedback resistor
between XIN and XOUT.
• Always supply XIN with the 12.288MHz or 24.576MHz clock set with XINSEL. If supplying other frequencies to
XIN, it is necessary to set that the result of change in sampling frequency fs of input data with FSERR is not reflected
to an error flag. By this setting, the operation functions properly. Since it is not a recommended frequency, it cannot
be used for input fs calculations.
• The setting of XINSEL must be completed prior to S/PDIF input.
• Supply XIN with clocks all the time to be used in the following applications.
(1) Detection of presence or absence of S/PDIF input
(2) Clock source while PLL is unlocked
(3) Calculation of input data sampling frequency
(4) Time definition when switching input data
(5) External source of supply clock (clock for an AD converter, etc.) in XIN source mode.
(6) Polling processing performed when setting the general-purpose I/O input function
• The oscillation amplifier runs even when the PLL is locked. Therefore, data detection and calculation of input
sampling frequency become possible while the PLL is locked. In that case, both the oscillation amplifier clock and the
PLL clock signals coexist, and then user must pay attention and make sure sound quality is not adversely affected.
• If adverse effects on the sound quality are recognized, it is possible to set with the AMPOPR [1:0] that the oscillation
amplifier automatically stop operation while the PLL is locked. Therefore, setting of the AMPOPR [1:0] must be
completed either prior to S/PDIF input or while PLL is unlocked.
• The oscillation amplifier can be stopped if it is unnecessary. However, when the normal operation is resumed, it must
wait for 10ms or longer until the resonator oscillation gets stable.
• XMCK outputs the XIN clock. The XMCK output is set with XMSEL [1:0]. The XIN clock can be set to 1/1, 1/2, 1/4,
or muted output.
• If you use only the oscillation amplifier, input the quartz resonator to XIN and XOUT or an external clock to XIN,
and fix the electric potential of digital data input pins of RX0 to RX6, or set with RISEL [2:0] that all the inputs are
deselected.
No.A1056-19/64