LC786821E Datasheet, PDF (4/35 Pages) ON Semiconductor – Compressed Audio Signal Processor IC

LC786821E
<Others>
 Watch Dog Timer
Notify to outside from the pin or internal reset.
 Sleep Mode (2 kinds)
(1) Only CPU core operates at slow clock and clocks for other blocks are stopped.
(2) All clocks are stopped by the main microcontroller control.
[ Useful functions for CD-DSP IC connection usage ]
<CD TEXT processing block>
 Buffers CD-TEXT data
 Starts buffering from desired ID3/ID4 of CD-TEXT data.
* Needs to connect subcode synchronization signals (SBSY and SFSY), shift clock (SBCK) and data (PW).
<CD-ROM processing block>
 Up to 4 speed operation available
 Supports CD-ROM decoding (Mode1, Mode2 <form1, form2>)
 Supports output of CD-ROM decoded data
* Needs to connect three signals (LRCK, BCK and DATA).
It is possible to connect C2 error flag if needed.
[ Others ]
<Internal power supply>
 Regulator for internal blocks (VDD for internal=1.2V, VDD for Flash=1.8V) built-in
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