LC786821E Datasheet, PDF (31/35 Pages) ON Semiconductor – Compressed Audio Signal Processor IC

PLL Circuit
Example of PLL circuit
LC786821E
LC786821E
VVDD2
AFILT
Cp2
Rp1
Cp1
 About PLL
LC786821E includes PLL1 and PLL2.
PLL1 is for generating system clock and PLL2 is for generating Audio clock.
 External filter constant for PLL2
PLL2 constant
Rp1=3.3kΩ / Cp1=3300pF / Cp2=220pF
<Notes>
 This PLL filter circuit of resistor (Rp1) and capacitance (Cp1, Cp2), are for audio generation/system clock
generation connected to AFILT. If oscillation clock is disturbed by noise or by the other factors, it may lead
to operation failure. Hence, make sure to connect resistor and capacitor that constitute filter circuit as close as
AFILT and the wire should be as short as possible. Also if filter constant changes due to temperature change,
oscillation of PLL may become unstable and the following problem may occur:
Due to unstable audio playback clock, audio playback is affected with unstable audio signal input (ADC
operation) and output (various filter, DAC operation). Hence, needs to select parts with caution so as to obtain
stable filter constant value within the guaranteed operating temperature range.
 See section on "Analog Pin Internal Equivalent Circuits" for the internal configuration of AFILT
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