PHU108NQ03LT Datasheet, PDF (7/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
2.5
V_GS(th)
(V)
2
1.5
1
03aa33
max
typ
min
10^-1
I_D
(A)
10^-2
10^-3
10^-4
03aa36
min
typ
max
0.5
10^-5
0
-60
0
60
120
180
T_j (°C)
10^-6
0
1
2
3
V_GS (V)
I_D = 1 mA; V_DS = V_GS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
T_j = 25 °C; V_DS = 5 V
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
10
V_GS
(V)
8
I_D = 25 A
T_j = 25 °C
03ar64
6
12 V
V_DS = 19 V
4
2
0
0
10
20
30 _{QG (nC)} 40
I_D = 25 A; V_DS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
V_DS
I_D
V_plat
V_GS(th)
V_GS
Q_gs1 Q_gs2
Q_gs
Q_gd
Q_g(tot)
003aaa508
Fig 12. Gate charge waveform definitions
9397 750 14707
Product data sheet
Rev. 03 — 18 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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