PHU108NQ03LT Datasheet, PDF (3/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
120
P_der
(%)
80
03aa16
120
I_der
(%)
80
03ar58
40
40
0
0
50
100
150
200
T_mb (°C)
P_der = _P--------^P----^t--^o--^t-------- × 100 %
tot(25 ^°C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
10³
I_D
(A)
10²
Limit R_DSon = V_DS / I_D
0
0
50
100
150
200
T_mb (°C)
I_der = -_I-------^I---^D--------- × 100 %
D(25 ^°C)
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
03ar59
t_p = 10 µs
100 µs
DC
1 ms
10
10 ms
1
1
10
V_DS (V)
10²
T_mb = 25 °C; I_DM is single pulse; V_GS = 5 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14707
Product data sheet
Rev. 03 — 18 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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