PHU108NQ03LT Datasheet, PDF (1/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
Rev. 03 — 18 April 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS™ technology.
1.2 Features
s Logic level threshold
s Lead-free construction
s Very low on-state resistance
s Low gate charge
1.3 Applications
s DC-to-DC converter
s Switch-mode power supplies
1.4 Quick reference data
s V_DS ≤ 25 V
s R_DSon ≤ 6 mΩ
s I_D ≤ 75 A
s Q_gd = 5.6 nC (typ)
2. Pinning information
Table 1: Pinning
Pin
Description
1
gate (G)
2
drain (D)
3
source (S)
mb
mounting base;
connected to drain
Simplified outline
[1]
mb
2
13
mb
2
1
3
SOT404 (D2PAK) SOT428 (DPAK)
[1] It is not possible to make a connection to pin 2 of the SOT404 and SOT428 packages.
Symbol
mb
D
G
mbb076 S
123
SOT533 (IPAK)