PHN203 Datasheet, PDF (7/13 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

NXP Semiconductors
80
R_DSon
(mΩ)
T_j = 25 °C
60
40
20
V_GS = 3.2 V
03ao27
3.4 V
3.6 V
4V
4.5 V
6V
10 V
0
0
10
20
30
I_D (A)
PHN203
Dual N-channel TrenchMOS logic level FET
2
03ad57
a
1.5
1
0.5
0
−60
0
60
120
180
T_j (°C)
Fig 9. Drain-source on-state resistance as a function Fig 10. Normalized drain-source on-state resistance
of drain current; typical values
factor as a function of junction temperature
10
V_GS
(V)
8
I_D = 7 A
Tj = 25 °C
V_DD = 15 V
6
4
03ae53
10³
C
(pF)
10²
03ae52
C_iss
C_oss
C_rss
2
0
0
5
10
15
Q_G (nC)
10
10^−1
1
10
10²
VDS (V)
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PHN203
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 27 April 2010
© NXP B.V. 2010. All rights reserved.
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