PHN203 Datasheet, PDF (1/13 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

PHN203
Dual N-channel TrenchMOS logic level FET
Rev. 05 — 27 April 2010
Product data sheet
1. Product profile
1.1 General description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Suitable for high frequency
applications due to fast switching
characteristics
„ Suitable for logic level gate drive
sources
1.3 Applications
„ DC-to-DC converters
„ Lithium-ion battery applications
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
Min Typ Max Unit
V_DS
drain-source
T_j ≥ 25 °C; T_j ≤ 150 °C
voltage
-
-
30 V
I_D
drain current
T_amb = 25 °C; pulsed;
[1] _-
-
6.3 A
see Figure 1; see Figure 3
P_tot
total power
T_amb = 25 °C; pulsed;
dissipation
see Figure 2
[1] _-
-
2W
Static characteristics
R_DSon
drain-source
on-state
resistance
V_GS = 10 V; I_D = 7 A; T_j = 25 °C;
see Figure 9; see Figure 10
-
24 30 mΩ
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 10 V; I_D = 7 A; V_DS = 15 V;
-
3-
nC
T_j = 25 °C; see Figure 11
[1] Single device conducting.