PHN203 Datasheet, PDF (2/13 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S1
source1
G1
gate1
S2
source2
G2
gate2
D2
drain2
D2
drain2
D1
drain1
D1
drain1
3. Ordering information
Simplified outline
8
5
Graphic symbol
D1 D1
D2 D2
1
4
SOT96-1 (SO8)
S1 G1 S2 G2
mbk725
Table 3. Ordering information
Type number
Package
Name
PHN203
SO8
4. Limiting values
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
V_DS
V_DGR
V_GS
I_D
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T_j ≥ 25 °C; T_j ≤ 150 °C
T_j ≤ 150 °C; T_j ≥ 25 °C; R_GS = 20 kΩ
T_amb = 70 °C; pulsed; see Figure 1
T_amb = 25 °C; pulsed; see Figure 1;
see Figure 3
I_DM
peak drain current
t_p ≤ 10 µs; pulsed; T_amb = 25 °C;
see Figure 3
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
T_amb = 25 °C; pulsed; see Figure 2
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_amb = 25 °C; pulsed
t_p ≤ 10 µs; pulsed; T_amb = 25 °C
E_DS(AL)S
non-repetitive
drain-source
avalanche energy
V_GS = 10 V; T_j(init) = 25 °C; I_D = 8.7 A;
V_sup ≤ 30 V; unclamped; t_p = 0.2 ms;
R_GS = 50 Ω
[1] Single device conducting.
PHN203
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 27 April 2010
Min Typ Max Unit
-
-
30 V
-
-
30 V
-20 -
20 V
[1] _-
-
5
A
[1] _-
-
6.3 A
[1] _-
-
18 A
[1] _-
-
-55 -
-55 -
2
W
150 °C
150 °C
[1] _-
-
2
A
[1] _-
-
4.1 A
-
-
37.8 mJ
© NXP B.V. 2010. All rights reserved.
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