PHN203 Datasheet, PDF (6/13 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
30
ID
(A)
T_j = 25 °C
20
03ao26
10 V 6 V 4.5 V 4 V
3.6 V
3.4 V
3.2 V
3V
10
2.8 V
2.6 V
V_GS = 2.4 V
0
0
0.5
1
1.5
V_DS (V)
30
I_D
(A)
V_DS > I_D x R_DSon
20
03ae49
10
0
0
150 °C
T_j = 25 °C
1
2
3
4
V_GS (V)
Fig 5. Output characteristics: drain current as a
Fig 6. Transfer characteristics: drain current as a
function of drain-source voltage; typical value
function of gate-source voltage; typical values
10^-1
I_D
(A)
10^-2
03aa36
2.5
V_GS(th)
(V)
2
max
03aa33
10^-3
min
typ
max
10^-4
1.5
typ
1
min
10^-5
0.5
10^-6
0
1
2
3
V_GS (V)
0
-60
0
60
120
180
T_j (°C)
Fig 7. Sub-threshold drain current as a function of
gate-source voltage
Fig 8. Gate-source threshold voltage as a function of
junction temperature
PHN203
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 27 April 2010
© NXP B.V. 2010. All rights reserved.
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