PHN203 Datasheet, PDF (3/13 Pages) NXP Semiconductors – Dual N-channel enhancement mode TrenchMOS transistor

NXP Semiconductors
PHN203
Dual N-channel TrenchMOS logic level FET
120
I_der
(%)
80
03aa19
120
P_der
(%)
80
03aa11
40
40
0
0
50
100
150
200
T_amb (°C)
0
0
50
100
150
200
T_amb (°C)
Fig 1. Normalized continuous drain current as a
function of ambient temperature
10²
I_D
(A)
10
Limit R_DSon = V_DS / I_D
Fig 2. Normalized total power dissipation as a
function of ambient temperature
03an69
t_p = 10 μs
1
10^−1
10^−2
10^−1
DC
1
1 ms
100 ms
1s
10 s
10
10²
V_DS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHN203
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 27 April 2010
© NXP B.V. 2010. All rights reserved.
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