74HCT9046A Datasheet, PDF (7/43 Pages) NXP Semiconductors – PLL with bandgap controlled VCO

NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
• The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input
(pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For
the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to
minimize standby power consumption.
8.2 VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one
external resistor R1 (between pins R1 and GND) or two external resistors R1 and R2
(between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine
the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset
if required (see Figure 4).
The high input impedance of the VCO simplifies the design of the low-pass filters by giving
the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. The
DEM_OUT voltage equals that of the VCO input. If DEM_OUT is used, a series resistor
(R_s) should be connected from pin DEM_OUT to GND; if unused, DEM_OUT should be
left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator
input (pin COMP_IN), or connected via a frequency divider. The output signal has a duty
cycle of 50 % (maximum expected deviation 1 %), if the VCO input is held at a constant
DC level. A LOW-level at the inhibit input (pin INH) enables the VCO and demodulator,
while a HIGH-level turns both off to minimize standby power consumption.
8.3 Phase comparators
The signal input (pin SIG_IN) can be directly coupled to the self-biasing amplifier at
pin SIG_IN, provided that the signal swing is between the standard HC family input logic
levels. Capacitive coupling is required for signals with smaller swings.
8.3.1 Phase Comparator 1 (PC1)
This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies
(f_i) must have a 50 % duty cycle to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (f_r = 2f_i) is suppressed, is:
V _{DEM _OUT} = ^V----_π-^C---^C--(Φ_{SIG_IN} – Φ_{COMP_IN})
where:
V_{DEM_OUT} is the demodulator output at pin DEM_OUT
V_{DEM_OUT} = V_{PC1_OUT} (via low-pass)
The phase comparator gain is: K _p = ^V----_π-^C---^C--(V ⁄ r)
The average output voltage from PC1, fed to the VCO input via the low-pass filter and
seen at the demodulator output at pin DEM_OUT (V_{DEM_OUT}), is the resultant of the phase
differences of signals (SIG_IN) and the comparator input (COMP_IN) as shown in
Figure 6. The average of V_{DEM_OUT} is equal to 0.5V_CC when there is no signal or noise at
SIG_IN and with this input the VCO oscillates at the center frequency (f₀). Typical
74HCT9046A_6
Product data sheet
Rev. 06 — 15 September 2009
© NXP B.V. 2009. All rights reserved.
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