74HCT9046A Datasheet, PDF (10/43 Pages) NXP Semiconductors – PLL with bandgap controlled VCO

NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
V_CC
up
I_cp
I_cp
down
PC2_OUT
C2
∆ Φ = Φ_{PC_IN}
pulse overlap of
approximately 15 ns
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a. At every ∆Φ, even at zero ∆Φ both switches are
closed simultaneously for a short period (typically
15 ns).
Fig 8. The current switch charge pump output of PC2
V_CC
up
down
R3'
PC2_OUT
Icp
VC2_OUT
C2
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b. Comparable voltage-controlled switch
+I_cp
V_CC
V_{DEM_OUT(AV)}
Icp × R
0
0.5V_CC
−I_cp
−2_π
a. Current transfer
0
Φ_{PC_IN}
+2_π
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pump current --^I2---^c-_π-^p-- Φ_{PC_IN}
0
−2_π
0
Φ_{PC_IN}
+2_π
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b. Voltage transfer. This transfer can be observed at
PC2_OUT by connecting a resistor (R = 10 kΩ)
between PC2_OUT and 0.5V_CC.
V _{DEM _OUT} = V _{PC2_OUT} = ₄--⁵--_π--Φ_{PC_IN}
Φ_{PC_IN} = (Φ_{SIG_IN} – Φ_{COMP_IN})
Fig 9. Phase comparator 2 current and voltage transfer characteristics
When the frequencies of SIG_IN and COMP_IN are equal but the phase of SIG_IN leads
that of COMP_IN, the up output driver at PC2_OUT is held ‘ON’ for a time corresponding
to the phase difference (Φ_{PC_IN}). When the phase of SIG_IN lags that of COMP_IN, the
down or sink driver is held ‘ON’.
74HCT9046A_6
Product data sheet
Rev. 06 — 15 September 2009
© NXP B.V. 2009. All rights reserved.
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