74HCT9046A Datasheet, PDF (11/43 Pages) NXP Semiconductors – PLL with bandgap controlled VCO

NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is
held ‘ON’ for most of the input signal cycle time and for the remainder of the cycle time
both drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN
frequency, then it is the sink driver that is held ‘ON’ for most of the cycle. Subsequently the
voltage at the capacitor (C2) of the low-pass filter connected to PC2_OUT varies until the
signal and comparator inputs are equal in both phase and frequency. At this stable point
the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at
pin 9 is a high-impedance. Also in this condition the signal at the phase comparator pulse
output (PCP_OUT) has a minimum output pulse width equal to the overlap time, so can be
used for indicating a locked condition.
Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full
frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is
reduced because both output drivers are OFF for most of the signal input cycle. It should
be noted that the PLL lock range for this type of phase comparator is equal to the capture
range and is independent of the low-pass filter. With no signal present at SIG_IN the VCO
adjust, via PC2, to its lowest frequency.
By using current sources as charge pump output on PC2, the dead zone or backlash time
could be reduced to zero. Also, the pulse widening due to the parasitic output capacitance
plays no role here. This enables a linear transfer function, even in the vicinity of the zero
crossing. The differences between a voltage switch charge pump and a current switch
charge pump are shown in Figure 11.
SIG_IN
COMP_IN
VCO_OUT
UP
DOWN
PC_IN
CURRENT AT
PC2_OUT
PC2_OUT/VCO_IN
high-impedance OFF-state,
(zero current)
15 ns typical
PCP_OUT
The pulse overlap of the up and down signals (typically 15 ns).
Fig 10. Timing diagram for PC2
mbd047
74HCT9046A_6
Product data sheet
Rev. 06 — 15 September 2009
© NXP B.V. 2009. All rights reserved.
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