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74HCT9046A Datasheet, PDF (34/43 Pages) NXP Semiconductors – PLL with bandgap controlled VCO | |||
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NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
74HCT9046A_6
Product data sheet
K p = 4-----Ã5-----Ï-- = 0.4 V â r
Using PC2 with the passive ï¬lter as shown in Figure 34 results in a high gain loop with the
same performance as a loop with an active ï¬lter. Hence loop ï¬lter equations as for a high
gain loop should be used. The current source output of PC2 can be simulated then with a
ï¬ctive ï¬lter resistance:
R3â = -R---1b---7i--a--s
The transfer functions of the ï¬lter is given by:
K f = 1-----+s---Ï--s-2--Ï--2-
Where:
Ï1 = R3â Ã C2
Ï2 = R4 Ã C2
The characteristic equation is: 1 + K p à K f à Ko à Kn
This results in:
1
+
K
p

ï£
1-----+s---Ï--s-1--Ï--2-
K-----v
s
K
n
=
0
or:
s2 + sK pK vK nÏÏ---21- + K pK vK n â Ï1 = 0
This can be written as:
s2 + 2ξÏns + (Ïn)2 = 0
with the natural frequency Ïn deï¬ned as:
Ïn = K-----p----Ã-----K-Ï--1--v---Ã-----K----n-
and the damping value given as: ζ = 0.5 à Ï2 à Ïn
In Figure 35 the output frequency response to a step of input frequency is shown.
The overshoot and settling time percentages are now used to determine Ïn.
From Figure 35 it can be seen that the damping ratio ζ = 0.707 will produce an overshoot
of less than 20 % and settle to within 5 % at Ïnt = 5. The required settling time is 1 ms.
This results in:
Rev. 06 â 15 September 2009
© NXP B.V. 2009. All rights reserved.
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