SI4410DY Datasheet, PDF (2/12 Pages) NXP Semiconductors – N-channel enhancement mode field-effect transistor

NXP Semiconductors
SI4410DY
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
S
source
2
S
source
3
S
source
4
G
gate
5
D
drain
6
D
drain
7
D
drain
8
D
drain
3. Ordering information
Simplified outline
8
5
1
4
SOT96-1 (SO8)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
SI4410DY
SO8
plastic small outline package; 8 leads; body width 3.9 mm
4. Limiting values
Version
SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
V_GS
gate-source voltage
I_D
drain current
T_amb = 70 °C; pulsed;
see Figure 1
T_amb = 25 °C; pulsed;
see Figure 1 and 3
I_DM
peak drain current
t_p ≤ 10 µs; T_amb = 25 °C; pulsed;
see Figure 3
P_tot
total power dissipation T_amb = 70 °C; pulsed;
see Figure 2
T_amb = 25 °C; pulsed;
see Figure 2
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
I_S
source current
T_amb = 25 °C; pulsed
Min Max Unit
-
30
V
-20 20
V
-
8
A
-
10
A
-
50
A
-
1.6 W
-
2.5 W
-55 150 °C
-55 150 °C
-
2.3 A
SI4410DY_3
Product data sheet
Rev. 03 — 4 December 2009
© NXP B.V. 2009. All rights reserved.
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