SE98A Datasheet, PDF (12/43 Pages) NXP Semiconductors – DDR memory module temp sensor, 1.7 V to 3.6 V

NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.7 SMBus Time-out
The SE98A supports the SMBus time-out feature. If the host holds SCL LOW between
25 ms and 35 ms, the SE98A would reset its internal state machine to the bus idle state to
prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out
is disabled by writing a logic 1 to bit 7 of register 22h.
Remark: When SMBus time-out is enabled, the I²C-bus minimum bus speed is limited by
the SMBus time-out timer, and goes down to only 10 kHz.
The SE98A has no SCL driver, so it cannot hold the SCL line LOW.
Remark: SMBus time-out works over the entire supply range of 1.7 V to 3.6 V unless
shutdown bit (SHMD) is set and turns off the oscillator.
7.8 SMBus ALERT
The SE98A supports SMBus ALERT when it is programmed for the Interrupt mode and
when the EVENT polarity bit is set to logic 0. The EVENT pin can be ANDed with other
EVENT or ALERT signals from other slave devices to signal their intention to
communicate with the host controller. When the host detects EVENT or ALERT signal
LOW, it issues an Alert Response Address (ARA) to which a slave device would respond
with its address. When there are multiple slave devices generating an ALERT the SE98A
performs bus arbitration. If it wins the bus, it responds to the ARA and then clears the
EVENT pin.
Remark: Either in comparator mode or when the SE98A crosses the critical temperature,
the host must also read the EVENT status bit and provide remedy to the situation by
bringing the temperature to within the alarm window or below the critical temperature if
that bit is set. Otherwise, the EVENT pin will not get de-asserted.
Remark: In the SE98A, the ARA is set to default ON. However, in the SE98B the ARA will
be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications.
START bit
read
Alert Response Address
acknowledge
not acknowledge STOP bit
device address
S 0 0 0 1 1 0 0 1 0 0 0 1 1 A2 A1 A0 0 1 P
host detects
SMBus ALERT
master sends a START bit,
ARA and a read command
Slave acknowledges and
sends its slave address.
The last bit of slave address
is hard coded '0'.
host NACK and
sends a STOP bit
002aab330
Fig 7. How SE98A responds to SMBus ALERT
SE98A_2
Product data sheet
Rev. 02 — 6 August 2009
© NXP B.V. 2009. All rights reserved.
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