DS90CR483 Datasheet, PDF (9/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

AC Timing Diagrams (Continued)
FIGURE 12. Receiver Power Down Delay
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C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) (Note 7) + ISI (Inter-symbol interference) (Note 8)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 7: Cycle-to-cycle LVDS Output jitter is less than 100 ps (worse case estimate).
Note 8: ISI is dependent on interconnect length; may be zero
FIGURE 13. Receiver Skew Margin
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