DS90CR483 Datasheet, PDF (14/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

Applications Information (Continued)
dure must be repeated or else the receiver may not sample
the incoming LVDS data correctly. When the receiver is in
the deskew mode, all receiver outputs are set to a LOW
state. Setting the “DESKEW” pin to low will disable the
deskew operation and allow the receiver to operation on a
fixed data sampling strobe. In this case, the ”DS_OPT” pin
on the transmitter must then be set high.
The DS_OPT pin at the input of the transmitter
(DS90CR483) is used to initiate the deskew calibration pat-
tern. It must be applied low for a minimum of four clock
cycles in order for the receiver to complete the deskew op-
eration. For this reason, the LVDS clock signal with DS_OPT
applied high (active data sampling) shall be 1111000 or
1110000 pattern. During the deskew operation with DS_OPT
applied low, the LVDS clock signal shall be 1111100 or
1100000 pattern. The transmitter will also output a series of
1111000 or 1110000 onto the LVDS data lines (TxOUT 0-7)
during deskew so that the receiver can automatically cali-
brated the data sampling strobes at the receiver inputs. Each
data channel is deskewed independently and is tuned with a
step size of 1/3 of a bit time over a range of +/−1 TBIT. The
Deskew feature operates up to clock rates of 80 MHz only.
When using the DESKEW feature, the sampling strobe will
remain within the middle third of the LVDS sub symbol.
The Receiver is also able to tolerate a maximum of 300ps
skew between the signals arriving on a single differential pair
(intra-pair).
Clock Jitter:
The transmitter is designed to reject cycle-to-cycle jitter
which may be seen at the transmitter input clock. Very low
cycle-to-cycle jitter is passed on to the transmitter outputs.
Cycle-to-cyle jitter has been measured over frequency is
less than 100 ps. This should be subtracted from the RSKM
budget as shown and described in Figure 13. This rejection
capability significantly reduces the impact of jitter at the TX-
input clock pin, and improves the accuracy of data sampling
in the receiver.
Power Down:
Both transmitter and receiver provide a power down feature.
When asserted current draw through the supply pins is mini-
mized and the PLLs are shut down. The transmitter outputs
are in TRI-STATE when in power down mode. The receiver
outputs are forced to a active LOW state when in the power
down mode. (See Pin Description Tables).
Configurations:
The transmitter is designed to be connected typically to a
single receiver load. This is known as a point-to-point con-
figuration. It is also possible to drive multiple receiver loads if
certain restrictions are made. Only the final receiver at the
end of the interconnect should provide termination across
the pair. In this case, the driver still sees the intended DC
load of 100 Ohms. Receivers connected to the cable be-
tween the transmitter and the final receiver must not load
down the signal. To meet this system requirement, stub
lengths from the line to the receiver inputs must be kept very
short.
Cable Termination
A termination resistor is required for proper operation to be
obtained. The termination resistor should be equal to the dif-
ferential impedance of the media being driven. This should
be in the range of 90 to 132 Ohms. 100 Ohms is a typical
value common used with standard 100 Ohm twisted pair
cables. This resistor is required for control of reflections and
also to complete the current loop. It should be placed as
close to the receiver inputs to minimize the stub length from
the resistor to the receiver input pins.
How to configure for backplane applications:
In a backplane application with differential line impedance of
100Ω the differential line pair-to-pair skew can controlled by
trace layout. The transmitter-DS90CR483 “DS_OPT” pin
may be set high. In a backplane application with short PCB
distance traces, pre-emphasis from the transmitter is typi-
cally not required. The “PRE” pin should be left open (do not
tie to ground). A resistor pad provision for a pull up resistor to
Vcc can be implemented in case pre-emphasis is needed to
counteract heavy capacitive loading effects.
How to configure for cable inter-connect applications:
In applications that require the long cable drive capability.
The DS90CR483/DS90CR484 chipset is improved over prior
generations of Channel Link devices and offers higher band-
width support and longer cable drive with the use of DC bal-
anced data transmission, pre-emphasis. Cable drive is en-
hanced with a user selectable pre-emphasis feature that
provides additional output current during transitions to coun-
teract cable loading effects. This requires the use of one pull
up resistor to Vcc; please refer to the table “Pre-emphasis
DC level with Rpre” above to set the level needed. DC bal-
ancing on a cycle-to-cycle basis, is also provided to reduce
ISI (Inter-Symbol Interference). With pre-emphasis and DC
balancing, a low distortion eye-pattern is provided at the re-
ceiver end of the cable. These enhancements allow cables
5+ meters in length to be driven. Depending upon clock rate
and the media being driven, the cable Deskew feature may
also be employed - see discussion on DESKEW above.
www.national.com
14