DS90CR483 Datasheet, PDF (4/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
LVDS RECEIVER DC SPECIFICATIONS
V_TH
Differential Input High V_CM = +1.2V
Threshold
V_TL
Differential Input Low
Threshold
I_IN
Input Current
TRANSMITTER SUPPLY CURRENT
V_IN = +2.4V, V_CC = 3.6V
V_IN = 0V, V_CC = 3.6V
ICCTW
Transmitter Supply
Current
Worst Case
R_L = 100Ω, C_L = 5 pF,
Worst Case Pattern
(Figures 1, 2)
f = 33 MHz
f = 66 MHz
f = 112 MHz
ICCTZ
Transmitter Supply
Current
Power Down
PD = Low
Driver Outputs in TRI-STATE under Powerdown
Mode
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply
Current
Worst Case
C_L = 8 pF,
Worst Case Pattern
(Figures 1, 3)
f = 33 MHz
f = 66 MHz
f = 112 MHz
ICCRZ
Receiver Supply
Current
Power Down
PD = LowReceiver Outputs stay low during
Power down mode.
Min
−100
Typ
91.4
106
155
5
125
215
350
20
Max Units
+100
mV
mV
±10
µA
±10
µA
140
mA
160
mA
190
mA
50
µA
150
mA
250
mA
380
mA
100
µA
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
TCIT
TxCLK IN Transition Time (Figure 4)
1.0
2.0
TCIP
TxCLK IN Period (Figure 5)
8.928
T
TCIH
TxCLK in High Time (Figure 5)
0.35T
0.5T
TCIL
TxCLK in Low Time (Figure 5)
0.35T
0.5T
TXIT
TxIN Transition Time
1.5
Max
3.0
30.3
0.65T
0.65T
6.0
Units
ns
ns
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time, (Figure 2),
0.14
PRE = 0.75V (disabled)
LVDS Low-to-High Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
LHLT
LVDS High-to-Low Transition Time, (Figure 2),
0.16
PRE = 0.75V (disabled)
LVDS High-to-Low Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
TBIT
Transmitter Bit Width
1/7 TCIP
TCCS
TxOUT Channel to Channel Skew
100
TSTC
TxIN Setup to TxCLK IN, (Figure 5)
2.5
THTC
TxIN Hold to TxCLK IN, (Figure 5)
0
TPDL
Transmitter Propagation Delay - Latency, (Figure 7) 1.5(TCIP)+3.72 1.5(TCIP)+4.4
TPLLS Transmitter Phase Lock Loop Set, (Figure 9)
TPDD
Transmitter Powerdown Delay, (Figure 11)
Max
0.7
0.6
0.8
0.7
1.5(TCIP)+6.24
10
100
Units
ns
ns
ns
ns
ns
ps
ns
ns
ns
ms
ns
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