DS90CR483 Datasheet, PDF (5/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RPDL
RPLLS
RPDD
RSKM
RDR
Parameter
CMOS/TTL Low-to-High Transition Time, (Figure 3),
Rx data out
CMOS/TTL Low-to-High Transition Time, (Figure 3),
Rx clock out
CMOS/TTL High-to-Low Transition Time, (Figure 3),
Rx data out
CMOS/TTL High-to-Low Transition Time, (Figure 3),
Rx clock out
RxCLK OUT Period, (Figure 6)
RxCLK OUT High Time, (Figure
6), (Note 4)
f = 112 MHz
f = 66 MHz
RxCLK OUT Low Time, (Figure 6), f = 112 MHz
(Note 4)
f = 66 MHz
RxOUT Setup to RxCLK OUT,
(Figure 6), (Note 4)
f = 112 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT,
(Figure 6), (Note 4)
f = 112 MHz
f = 66 MHz
Receiver Propagation Delay - Latency, (Figure 8)
Receiver Phase Lock Loop Set ,(Figure 10)
Receiver Powerdown Delay, (Figure 12)
Receiver Skew Margin without
Deskew, (Figure 13), (Notes 4, 5)
f = 112 MHz
f = 85 MHz
f = 66 MHz
Receiver Deskew Range
f = 80 MHz
RDSS
Receiver Deskew Step Size
f = 80 MHz
Min
8.928
3.5
6.0
3.5
6.0
2.4
3.6
3.4
7.0
3(TCIP)+4.0
170
160
210
± 1.786
(± 1TBIT)
Typ
T
3(TCIP)+4.8
210
200
275
(± 1.3 TBIT)
0.3 TBIT
Max
Units
2.0
ns
1.0
ns
2.0
ns
1.0
ns
30.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
3(TCIP)+6.5
ns
10
ms
1
µs
ps
ps
ps
ns
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T _A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_TH, V_TL, V_OD and ∆V_OD).
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is func-
tionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional perfor-
mance.
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
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