DS90CR483 Datasheet, PDF (12/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

DS90CR484 Pin Description—Channel Link Receiver
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
No.
Description
I
8
Positive LVDS differential data inputs.
I
8
Negative LVDS differential data inputs.
O
48
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs
are forced to a Low state.
I
1
Positive LVDS differential clock input.
I
1
Negative LVDS differential clock input.
O
1
TTL level clock output. The rising edge acts as data strobe.
I
1
PLL range select. This pin must be tied to V_CC. NC or tied to Ground is
reserved for future use. (Note 9)
I
1
Deskew / Oversampling “on/off” select. When using the Deskew /
Oversample feature this pin must be tied to V_CC. Tieing this pin to ground
disables this feature. (Note 9)
I
1
TTL level input. When asserted (low input) the receiver outputs are Low.
(Note 9)
I
8
Power supply pins for TTL outputs and digital circuitry.
I
8
Ground pins for TTL outputs and digital circuitry.
I
1
Power supply for PLL circuitry.
I
2
Ground pin for PLL circuitry.
I
2
Power supply pin for LVDS inputs.
I
3
Ground pins for LVDS inputs.
6
No Connect. Make NO Connection to these pins - leave open.
Note 10: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions re-
ceiver inputs will be in a HIGH state. If the cable inter-connect are disconnected which results in floating/terminated inputs, the outputs will remain in the last valid
state.
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