DS90CR483 Datasheet, PDF (13/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

Applications Information
The DS90CR483/DS90CR484 chipset is improved over prior
generations of Channel Link devices and offers higher band-
width support and longer cable drive with three areas of en-
hancement. To increase bandwidth, the maximum clock rate
is increased to 112 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. This
requires the use of one pull up resistor to Vcc; please refer to
the table “Pre-emphasis DC level with Rpre” below to set the
level needed. DC balancing on a cycle-to-cycle basis, is also
provided to reduce ISI (Inter-Symbol Interference). With
pre-emphasis and DC balancing, a low distortion eye-pattern
is provided at the receiver end of the cable. A cable deskew
capability has been added to deskew long cables of
pair-to-pair skew of up to +/−1 LVDS data bit time (up to 80
MHz clock rates). For detail on deskew, refer to “Deskew”
section of this application information. These three enhance-
ments allow cables 5+ meters in length to be driven.
New features Description:
1. Pre-emphasis: Adds extra current during LVDS logic tran-
sition to reduce the cable loading effects. Pre-emphasis
strength is set via a DC voltage level applied from min to max
(0.75V to Vcc) at the “PRE” pin. A higher input voltage on the
”PRE” pin increases the magnitude of dynamic current dur-
ing data transition. The “PRE” pin requires one pull-up resis-
tor (Rpre) to Vcc in order to set the DC level. There is an in-
ternal resistor network, which cause a voltage drop. Please
refer to the tables below to set the voltage level.
TABLE 1. Pre-emphasis DC voltage level with (Rpre)
Rpre
1MΩ or NC
50kΩ
9kΩ
3kΩ
1kΩ
100Ω
Resulting PRE Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Effects
Standard LVDS
50% pre-emphasis
100% pre-emphasis
TABLE 2. Pre-emphasis needed per cable length
Frequency
112MHz
112MHz
80MHz
80MHz
66MHz
PRE Voltage
1.0V
1.5V
1.0V
1.2V
1.5V
Typical cable length
2 meters
5 meters
2 meters
5+ meters
5+ meters
Note 11: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating
frequency.
2. DC Balance: In addition to data information an additional
bit is transmitted on every LVDS data signal line during each
cycle as shown in Figure 14. This bit is the DC balance bit
(DCBAL). The purpose of the DC Balance bit is to minimize
the short- and long-term DC bias on the signal lines. This is
achieved by selectively sending the data either unmodified
or inverted.
The value of the DC balance bit is calculated from the run-
ning word disparity and the data disparity of the current word
to be sent. The data disparity of the current word shall be cal-
culated by subtracting the number of bits of value 0 from the
number of bits value 1 in the current word. Initially, the run-
ning word disparity may be any value between +7 and −6.
The running word disparity shall be calculated as a continu-
ous sum of all the modified data disparity values, where the
unmodified data disparity value is the calculated data dispar-
ity minus 1 if the data is sent unmodified and 1 plus the in-
verse of the calculated data disparity if the data is sent in-
verted. The value of the running word disparity shall saturate
at +7 and −6.
The value of the DC balance bit (DCBAL) shall be 0 when
the data is sent unmodified and 1 when the data is sent in-
verted. To determine whether to send data unmodified or in-
verted, the running word disparity and the current data dis-
parity are used. If the running word disparity is positive and
the current data disparity is positive, the data shall be sent
inverted. If the running word disparity is positive and the cur-
rent data disparity is zero or negative, the data shall be sent
unmodified. If the running word disparity is negative and the
current data disparity is positive, the data shall be sent un-
modified. If the running word disparity is negative and the
current data disparity is zero or negative, the data shall be
sent inverted. If the running word disparity is zero, the data
shall be sent inverted.
Cable drive is enhanced with the user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided to re-
duce ISI (Inter-Symbol Interference). With pre-emphasis and
DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. These enhancements allow cables
5+ meters in length to be driven depending upon media and
clock rate.
3. Deskew: The “DESKEW” pin on the receiver when set
high will deskew a minimum of ±1 LVDS data bit time skew
between signals arriving on independent differential pairs
(pair-to-pair skew). It is required that the “DS_OPT” pin on
the Transmitter must be applied low for a minimum of four
clock cycles to complete the deskew operation. It is also re-
quired that this must be performed at least once at any time
after the PLL has locked to the input clock frequency. If
power is lost, or if the cable has been switched, this proce-
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