DS90CR483 Datasheet, PDF (11/17 Pages) National Semiconductor (TI) – 48-Bit LVDS Channel Link Serializer/Deserializer

DS90CR483 Pin Description—Channel Link Transmitter
Pin Name
TxIN
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
I/O
No.
Description
I
48
TTL level input. (Note 9).
O
8
Positive LVDS differential data output.
O
8
Negative LVDS differential data output.
I
1
TTL level clock input. The rising edge acts as data strobe.
O
1
Positive LVDS differential clock output.
TxCLKM
PD
PLLSEL
PRE
DS_OPT
V_CC
GND
PLLV_CC
PLLGND
O
1
Negative LVDS differential clock output.
I
1
TTL level input. Assertion (low input) tri-states the outputs, ensuring low
current at power down. (Note 9).
I
1
PLL range select. This pin must be tied to V_CC. NC or tied to Ground is
reserved for future use. (Note 9)
I
1
Pre-emphasis “level” select. Pre-emphasis is active when input is tied to
V_CC through external pull-up resistor. Resistor value determines
Pre-emphasis level (See Applications Information Section). For normal
LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to
ground).
I
1
Cable Deskew performed when TTL level input is low. No TxIN data is
sampled during Deskew. To perform Deskew function, input must be held
low for a minimum of 4 clock cycles. The Deskew operation is normally
conducted after the TX and RX PLLs have locked. It should also be
conducted after a system reset, or a reconfiguration event. It must be
peformed at least once when ″DESKEW″ is enabled. (Note 9)
I
8
Power supply pins for TTL inputs and digital circuitry.
I
5
Ground pins for TTL inputs and digital circuitry.
I
2
Power supply pin for PLL circuitry.
I
3
Ground pins for PLL circuitry.
LVDSV_CC
LVDSGND
NC
I
3
Power supply pin for LVDS outputs.
I
4
Ground pins for LVDS outputs.
4
No Connect. Make NO Connection to these pins - leave open.
Note 9: Inputs default to “low” when left open due to internal pull-down resistor.
11
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