DS90C3202 Datasheet, PDF (9/22 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

AC Timing Diagrams (Continued)
FIGURE 9. RFB: LVTTL Level Programmable Strobe Select
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RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Please see National’s AN-1217 for more details.
Note 11: Cycle-to-cycle jitter is less than 100 ps (worse case estimate).
Note 12: ISI is dependent on interconnect length; may be zero.
FIGURE 10. Receiver Input Tolerance and Sampling Window
Register address 29d/1dh bit [2:1] = 00b
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FIGURE 11. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled
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