DS90C3202 Datasheet, PDF (5/22 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Condition/
Min
Reference
CLHT
LVCMOS/LVTTL Low-to-High Transition
Time, C_L = 8pF, (Figure 5) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
Rx data out
CHLT
LVCMOS/LVTTL High-to-Low Transition
Time, C_L = 8pF, (Figure 5) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
Rx data out
CLHT
Programmable
adjustment
LVCMOS/LVTTL Low-to-High Transition
Time, C_L = 8pF, (Figure 5) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
Rx clock out
Rx data out
CHLT
Programmable
adjustment
LVCMOS/LVTTL High-to-Low Transition
Time, C_L = 8pF, (Figure 5) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
Rx data out
RCOP
RCLK OUT Period (Figures 11, 12) (Note 8) 8–135 MHz
7.4
RCOH
RCLK OUT High Time (Figures 11, 12)
Rx clock out
0.4T
RCOL
RCLK OUT Low Time (Figures 11, 12)
Rx clock out
0.4T
RSRC
RxOUT Setup to RCLK OUT (Figures 11, 12) (Notes 8, 9)
2.60
Register addr 29d/1dh [2:1]= 00b (Default)
RHRC
RxOUT Hold to RCLK OUT (Figures 11, 12) (Notes 8, 9)
3.60
Register addr 29d/1dh [2:1]= 00b (Default)
RSRC/RHRC
Programmable
Adjustment
Register addr 29d/1dh [2:1] = 01b, (Figures 13, 14)
(Notes 2, 10)
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
Register addr 29d/1dh [2:1] = 10b, (Figures 13, 14)
(Notes 2, 10)
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
Register addr 29d/1dh [2:1] = 11b, (Figures 13, 14)
(Notes 2, 10)
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
RPLLS
Receiver Phase Lock Loop Set (Figure 6)
RPDD
Receiver Powerdown Delay (Figure 7)
RPDL
Receiver Propagation Delay — Latency (Figure 8)
RITOL
Receiver Input Tolerance
(Figures 10, 16) (Notes 8, 10)
V_CM = 1.25V,
V_ID = 350mV
Typ
Max
1.45
2.10
2.40
3.50
1.35
2.20
2.40
3.60
2.45
3.40
2.35
3.40
T
0.5T
0.5T
0.5T
0.5T
+1UI /
-1UI
125
0.6T
0.6T
-1UI /
+1UI
+2UI /
-2UI
10
100
4*RCLK
0.25
Note 8: Specification is guaranteed by characterization.
Note 9: A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
Note 10: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
UI
5
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