DS90C3202 Datasheet, PDF (17/22 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202 Pin Descriptions (Continued)
Pin No.
92
93
94
95
Pin Name
RXOA4
RXOA5
RXOA6
VDD5
I/O
O/P
O/P
O/P
VDD
Pin Type
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
96
VSS5
GND LVTTL O/P PWR
97
RESRVD
I/P
LVTTL I/P (pulldown)
98
MODE1
I/P
Digital (pulldown)
99
VSSL
GND LVDS PWR
100
VDDL
VDD LVDS PWR
101
RXOA-
I/P
LVDS I/P
102
RXOA+
I/P
LVDS I/P
103
RXOB-
I/P
LVDS I/P
104
RXOB+
I/P
LVDS I/P
105
RXOC-
I/P
LVDS I/P
106
RXOC+
I/P
LVDS I/P
107
RXOD-
I/P
LVDS I/P
108
RXOD+
I/P
LVDS I/P
109
RXOE-
I/P
LVDS I/P
110
RXOE+
I/P
LVDS I/P
111
VSSL
GND LVDS PWR
112
VSSL
GND LVDS PWR
113
VDDL
VDD LVDS PWR
114
VDDL
VDD LVDS PWR
115
RCLKIN-
I/P
LVDS I/P
116
RCLKIN+
I/P
LVDS I/P
117
RXEA-
I/P
LVDS I/P
118
RXEA+
I/P
LVDS I/P
119
RXEB-
I/P
LVDS I/P
120
RXEB+
I/P
LVDS I/P
121
RXEC-
I/P
LVDS I/P
122
RXEC+
I/P
LVDS I/P
123
RXED-
I/P
LVDS I/P
124
RXED+
I/P
LVDS I/P
125
RXEE-
I/P
LVDS I/P
126
RXEE+
I/P
LVDS I/P
127
MODE0
I/P
Digital (pulldown)
128
RFB
I/P
Digital (pulldown)
Description
LVTTL level data output
LVTTL level data output
LVTTL level data output
Power supply pin for LVTTL outputs and digital
circuitry
Ground pin for LVTTL outputs and digital circuitry
Tie to VSS for correct functionality
“ODD” Bank Enable
0 = LVTTL ODD OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL ODD OUTPUTS ENABLED
Ground pin for LVDS
Power supply pin for LVDS
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Ground pin for LVDS
Ground pin for LVDS
Power supply pin for LVDS
Power supply pin for LVDS
Negative LVDS differential clock input
Positive LVDS differential clock input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
“EVEN” Bank Enable
0 = LVTTL EVEN OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL EVEN OUTPUTS ENABLED
Rising Falling Bar (Figure 9)
0 = FALLING EDGE DATA STROBE
1 = RISING EDGE DATA STROBE
17
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