DS90C3202 Datasheet, PDF (4/22 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current
Worst Case
(Figures 2, 4)
C_L = 8 pF,
Worst Case
Pattern
Default Register
Settings
f = 8 MHz
f = 135 MHz
65
130
mA
375
550
mA
ICCRG
Receiver Supply Current
Incremental Test Pattern
(Figures 3, 4)
C_L = 8 pF,
Worst Case
Pattern
Default Register
Settings
f = 8 MHz
f = 135 MHz
55
120
mA
245
400
mA
ICCRZ
Receiver Supply Current
Power Down
PDWNB = Low
Receiver Outputs stay low
during Powerdown mode.
Default Register Settings
2
mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_DD = 3.3V and T _A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified.
Note 4: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Note 5: The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Note 6: Figures 2, 3 show a falling edge data strobe (RCLK OUT).
Note 7: Figure 8 show a rising edge data strobe (RCLK OUT).
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