DS90C3202 Datasheet, PDF (19/22 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202 Two-Wire Serial Interface Register Table
Address
0d/0h
1d/1h
2d/2h
3d/3h
4d/4h
5d/5h
6d/6h
7d/7h
8d/8h
9d/9h
10d/ah
11d/bh
R/W
R
R
R
R
R
R
R
R
R
R
R
R
RESET
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
Bit #
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Description
Vender ID low byte[7:0] = 05h
Vender ID high byte[15:8] =13h
Device ID low byte[7:0] = 28h
Device ID high byte 15:8] = 67h
Device revision [7:0] = 00h to begin with
Low frequency limit, 8Mhz = 8h
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
Reserved
Reserved
Reserved
Reserved
Reserved
Default Value
0000_0101
0001_0011
0010_1000
0110_0111
0000_0000
0000_1000
1000_0111
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
20d/14h
R/W
21d/15h
R/W
22d/16h
R/W
23d/17h
R/W
24d/18h
R/W
25d/19h
R/W
None
None
None
None
None
None
[7:0] Reserved
0000_0000
[7:0] Reserved
0000_0000
[7:3] Reserved
0000_0000
[2:0] LVDS input skew control for CLK channel,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Tsetup improvement
[7]
Reserved
0000_0000
[6:4] LVDS input skew control for RXO channel B,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
[3]
Reserved
[2:0] LVDS input skew control for RXO channel C,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
[7]
Reserved
0000_0000
[6:4] LVDS input skew control for RXO channel D,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
[3]
Reserved
[2:0] LVDS input skew control for RXO channel E,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
[7]
Reserved
0000_0000
[6:4] LVDS input skew control for RXO channel A,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
[3]
Reserved
[2:0] LVDS input skew control for RXE channel A,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
19
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