DS16EV5110_0706 Datasheet, PDF (9/18 Pages) National Semiconductor (TI) – Video Equalizer for DVI, HDMI, and Cat5 Cables

DS16EV5110 Device Description
The DS16EV5110 video equalizer comprises three data
channels, a clock channel, and a control interface including a
Serial Management Bus (SMBus) port.
DATA CHANNELS
The DS16EV5110 provides three data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a TMDS driver as shown in
Figure 2.
FIGURE 2. DS16EV5110 Data Channel
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EQUALIZER BOOST CONTROL
The data channel equalizers support eight programmable lev-
els of equalization boost. The state of the FEB pin determines
how the boost settings are controlled. If the FEB pin is held
High, then the equalizer boost setting is controlled by the
Boost Set pins (BST_[0:2]) in accordance with Table 2. If this
programming method is chosen, then the boost setting se-
lected on the Boost Set pins is applied to all three data
channels. When the FEB pin is held Low, the equalizer boost
level is controlled through the SMBus. This programming
method is accessed via the appropriate SMBus registers (see
Table 1). Using this approach, equalizer boost settings can
be programmed for each channel individually. FEB is inter-
nally pulled High (default setting); therefore if left unconnect-
ed, the boost settings are controlled by the Boost Set pins
(BST_[0:2]). The range of boost settings provided enables the
DS16EV5110 to address a wide range of transmission line
path loss scenarios, enabling support for a variety of data
rates and formats.
TABLE 2. EQ Boost Control Table
Control Via
SMBus
BC_2, BC_1,
BC_0
(FEB = 0)
Control Via Pins
BST_2, BST_1,
BST_0
(FEB = 1)
EQ Boost Setting
at 825 MHz (dB)
000
000
9
001
001
14
010
010
18
011
011
21
100
100
24
101
101
26
110
110
28
111
111
30
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