DS16EV5110_0706 Datasheet, PDF (5/18 Pages) National Semiconductor (TI) – Video Equalizer for DVI, HDMI, and Cat5 Cables

Symbol
Parameter
t_D
Latency
OUTPUT JITTER
TJ1
Total Jitter at 1.65 Gbps
TJ2
Total Jitter at 2.25 Gbps
TJ3
Total Jitter at 165 MHz
TJ4
Total Jitter at 225 MHz
RJ
BIT RATE
F_CLK
BR
Random Jitter
Clock Frequency
Bit Rate
Conditions
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7
(Notes 5, 6, 7)
20m 28 AWG STP DVI Cable
Data Paths
EQ Setting 0x04 PRBS7
(Notes 5, 6, 7)
Clock Paths
Clock Pattern
(Notes 5, 6, 7)
Clock Paths
Clock Pattern
(Notes 5, 6, 7)
(Notes 7, 8)
Clock Path
(Note 5)
Data Path
(Note 5)
Min
Typ
Max
Units
350
ps
0.13
0.17
UI_P-P
0.2
UI_P-P
0.165
UI_P-P
0.165
3
UI_P-P
psrms
25
225
MHz
0.25
2.25
Gbps
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at V_DD = 3.3V, T_A = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mV_P-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (TPC of Figure 1), minus the deterministic jitter before the test channel (TPA of Figure 1). Random
jitter is removed through the use of averaging or similar means.
Note 7: Total Jitter is defined as peak-to-peak deterministic jitter from (Note 8) + 14.2 times random jitter.
Note 8: Random jitter contributed by the equalizer is defined as sq rt (J_OUT2 − J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see TPC of Figure
1; J_IN is the random jitter at the input of the equalizer in ps-rms, see TPA of Figure 1.
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