DS16EV5110_0706 Datasheet, PDF (7/18 Pages) National Semiconductor (TI) – Video Equalizer for DVI, HDMI, and Cat5 Cables

Serial Management Bus (SMBus)
Configuration Registers
The Serial Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification, except for bus termina-
tion voltages. Holding the CS pin High enables the SMBus
port allowing access to the SMBus registers. The configura-
tion registers can be read and written using SMBus through
the SDA and SDC pins. In the STANDBY state, the Serial
Management Bus remains active. Please see Table 1 for
more information.
TABLE 1. SMBus Register Address
Name
Address Default Type Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Status
0x00
0x00 RO ID Revision
Reserved Reserved Reserved SD
Status
0x01
0x00 RO Reserved Boost 1
EN
Reserved
Status
0x02
0x00 RO Reserved Boost 3
Reserved Boost 2
Internal
Enable/
Individual
Channel
Boost
Control
for
C_IN±,
D_IN0±
0x03
0x77
RW EN (Int.) Boost Control
0:Enable (BC for CH0)
1:Disable 000 (Min Boost)
(D_IN0±) 001
010
011
100
101
110
111 (Max Boost)
EN (Int.)
0:Enable
1:Disable
(C_IN±)
Reserved
Individual
Channel
Boost
Control
for
D_IN1±,
D_IN2±
0x04
0x77
RW EN (Int.) Boost Control
0:Enable (BC for CH2)
1:Disable 000 (Min Boost)
(D_IN2±) 001
010
011
100
101
110
111 (Max Boost)
EN (Int.)
0:Enable
1:Disable
(D_IN1±)
Boost Control
(BC for CH1)
000 (Min Boost)
001
010
011
100
101
110
111 (Max Boost)
Signal
0x05
Detect ON
(SD_ON)
0x00 RW Reserved
Threshold (mV)
00: 70 (Default)
01: 55
10: 90
11: 75
Signal
0x06
Detect OFF
(SD_OFF)
0x00 RW Reserved
Threshold (mV)
00: 40 (Default)
01: 30
10: 55
11: 45
SMBus or 0x07
CMOS
Control for
EN
0x00 RW Reserved
SMBus
Enable
0: Disable
1: Enable
Output
Level
0x08
0x78 RW Reserved
Output Level:
00: 540 mVp-p
01: 770 mVp-p
10: 1000 mVp-p
11: 1200 mVp-p
Reserved
Note: RO = Read Only, RW = Read/Write
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