DS16EV5110_0706 Datasheet, PDF (13/18 Pages) National Semiconductor (TI) – Video Equalizer for DVI, HDMI, and Cat5 Cables

TABLE 6. Boost Control Setting for STP Cables
Setting Data Rate
28 AWG DVI / HDMI
0x04
750 Mbps
0–25m
0x04 1.65 Gbps
0–20m
0x06
750 Mbps
25m to greater than 30m
0x06 1.65 Gbps
20m to greater than 25m
0x03 2.25 Gbps
0–15m
0x06 2.25 Gbps
15m to greater than 20m
UTP (UNSHIELDED TWIST PAIRS) CABLES
The DS16EV5110 can be used to extend the length of UTP
cables, such as Cat5, Cat5e and Cat6 to distances greater
than 20 meters at 1.65 Gbps with < 0.13 UI of jitter. Please
note that for non-standard DVI/HDMI cables, the user must
ensure the clock-to-data channel skew requirements are met.
Table 7 presents the recommended boost control settings for
various data rates and cable lengths for UTP configurations:
TABLE 7. Boost Control Setting for UTP Cables
Setting
Data Rate
Cat5 Cable
0x03
750 Mbps
0–25m
0x06
750 Mbps
25–45m
0x03
1.65 Gbps
Greater than 20m
CABLE SELECTION
At higher frequencies, longer cable lengths produce greater
losses due to the skin effect. The quality of the cable with
respect to conductor wire gauge and shielding heavily influ-
ences performance. Thicker conductors have lower signal
degradation per unit length. In nearly all applications, the
DS16EV5110 equalization can be set to 0x04, and equalize
up to 22 dB skin effect loss for all input cable configurations
at all data rates, without degrading signal integrity.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The TMDS differential inputs and outputs must have a con-
trolled differential impedance of 100Ω. It is preferable to route
TMDS lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if pos-
sible. If vias must be used, they should be used sparingly and
must be placed symmetrically for each side of a given differ-
ential pair. Route the TMDS signals away from other signals
and noise sources on the printed circuit board. All traces of
TMDS differential inputs and outputs must be equal in length
to minimize intra-pair skew.
See AN-1187 for additional information on LLP packages.
General Recommendations
The DS16EV5110 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the LVDS
Owner’s Manual for more detailed information on high-speed
design tips as well as many other available resources avail-
able addressing signal integrity design issues.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS16EV5110 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01µF bypass ca-
pacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS16EV5110.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2µF to 10µF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS16EV5110.
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