DS16EV5110_0706 Datasheet, PDF (2/18 Pages) National Semiconductor (TI) – Video Equalizer for DVI, HDMI, and Cat5 Cables

Pin Descriptions
Pin Name Pin Number I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
C_IN−
C_IN+
1
I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50Ω terminating
2
resistor connects C_IN+ to VDD and C_IN- to VDD.
D_IN0−
D_IN0+
4
I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
5
resistor connects D_IN0+ to VDD and D_IN0- to VDD.
D_IN1−
D_IN1+
8
I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
9
resistor connects D_IN1+ to VDD and D_IN1- to VDD.
D_IN2−
D_IN2+
11
I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
12
resistor connects D_IN2+ to VDD and D_IN2- to VDD.
C_OUT-
C_OUT+
36
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
35
D_OUT0−
33
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0+
32
D_OUT1–
29
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT1+
28
D_OUT2−
26
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT2+
25
Equalization Control
BST_0
BST_1
BST_2
23
I, CMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0,
14
BST_1, and BST_2 are internally pulled Low.
37
Device Control
EN
44
I, CMOS Enable Equalizer inputs. When held High, normal operation is selected. When held Low,
standby mode is selected. EN is internally pulled High.
FEB
21
I, CMOS Force External Boost. When held High, the equalizer boost setting is controlled by the BST_
[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus (see
Table 1) control pins. FEB is internally pulled High.
SD
45
O, CMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.
POWER
V_DD
3, 6, 7,
I, Power V_DD pins should be tied to the V_DD plane through a low inductance path. A 0.01µF bypass
10, 13,
capacitor should be connected between each V_DD pin to the GND planes.
15, 46
GND
22, 24,
27, 30,
31, 34
I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed
Pad
PAD
I, Power The exposed pad at the center of the package must be connected to the ground plane.
Serial Management Bus (SMBus) Interface Control Pins
SDA
SDC
CS
18
I, CMOS Data Input. Internally pulled High.
17
I, CMOS Clock Input. Internally pulled High.
16
I, CMOS Chip select. When held High, the equalizer SMBus register is enabled. When held Low, the
equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally gated with
SDC.
Other
Reserv
19, 20, 38,
39, 40,41,
42, 43, 47,
48
Reserved. Do not connect.
Note: I = Input O = Output
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