DS16EV5110_0706 Datasheet, PDF (11/18 Pages) National Semiconductor (TI) – Video Equalizer for DVI, HDMI, and Cat5 Cables

OUTPUT LEVEL CONTROL
The output amplitude of the TMDS drivers for both the data
channels and the clock channel can be controlled via the SM-
Bus (see Table 1). The default output level is 1000mV p-p.
The following Table presents the output level values support-
ed:
TABLE 5. Output Level Control Settings
Bit 3
Bit 2
Output Level (mV)
0
0
540
0
1
770
1
0
1000 (default)
1
1
1200
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110 to be configured to
automatically enter STANDBY mode if no clock signal is
present. STANDBY mode can be implemented by connecting
the Signal Detect (SD) pin to the external (CMOS) Enable
(EN) pin. In order for this option to function properly, the FEB
pin must be either tied High or not connected (the FEB pin is
internally pulled High by default). If the clock signal applied to
the clock channel input swings above the maximum level
specified in the threshold register via the SMBus, then the SD
pin is asserted High. If the SD pin is connected to the EN pin,
this will enable the equalizer, limiting amplifier, and output
buffer on the data channels and the limiting amplifier and out-
put buffer on the clock channel (provided that the FEB pin is
High); thus the DS16EV5110 will automatically enter the AC-
TIVE state. If the clock signal present falls below the minimum
level specified in the threshold register, then the SD pin will
be asserted Low, causing the aforementioned blocks to be
placed in the STANDBY state.
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