COPC912C Datasheet, PDF (9/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller

Functional Description (Continued)
EXTERNAL EVENT COUNTER MODE
In this mode the timer becomes a 16-bit external event
counter clocked from an input signal applied to the G3 in-
put The maximum frequency for this G3 input clock is
250 kHz (half of the 0 5 MHz instruction cycle clock) When
the external event counter underflows the value in the au-
toreload register is copied into the timer This timer under-
flow may also be used to generate an interrupt Bit 5 of the
CNTRL register is used to select whether the external event
counter clocks on positive or negative edges from the G3
input Consequently half cycles of an external input signal
could be counted The External Event counter mode is
shown in Figure 8
grammed to generate an interrupt The duration of an input
signal can be computed by capturing the time of the leading
edge saving this captured value changing the capture
edge capturing the time of the trailing edge and then sub-
tracting this trailing edge time from the earlier leading edge
time The Input Capture mode is shown in Figure 9
TL DD 12060 – 11
FIGURE 8 Timer in External Event Mode
INPUT CAPTURE MODE
In this mode the timer counts down at the instruction clock
rate When an external edge occurs on pin G3 the value in
the timer is copied into the capture register Consequently
the time of an external edge on the G3 pin is ‘‘captured’’ Bit
5 of the CNTRL register is used to select the polarity of the
external edge This external edge capture can also be pro-
TL DD 12060 – 12
FIGURE 9 Timer in Input Capture Mode
Table IV below details the TIMER modes of operation and
their associated interrupts Bit 4 of CNTRL is used to start
and stop the timer counter Bits 5 6 and 7 of the CNTRL
register select the timer modes The ENTI (Enable Timer
Interrupt) and TPND (Timer Interrupt Pending) bits in the
PSW register are used to control the timer interrupts
Care must be taken when reading from and writing to the
timer and its associated autoreload capture register The
timer and autoreload capture register are both 16-bit but
they are read from and written to one byte at a time It is
recommended that the timer be stopped before writing a
new value into it The timer may be read ‘‘on the fly’’ without
stopping it if suitable precautions are taken One method of
reading the timer ‘‘on the fly’’ is to read the upper byte of the
timer first and then read the lower byte If the most signifi-
cant bit of the lower byte is then tested and found to be
high then the upper byte of the timer should be read again
and this new value used
CNTRL Bits
7
6
5
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TABLE IV Timer Modes and Control Bits
Operation Mode
Timer
Interrupt
External Event Counter with Autoreload Register
External Event Counter with Autoreload Register
Not Allowed
Not Allowed
Timer with Autoreload Register
Timer with Autoreload Regiter and Toggle TIO Out
Timer with Capture Register
Timer with Capture Register
Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TIO Positive Edge
TIO Negative Edge
Timer
Counts On
TIO Positive Edge
TIO Negative Edge
Not Allowed
Not Allowed
tc
tc
tc
tc
9
http www national com