COPC912C Datasheet, PDF (11/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller

Interrupts (Continued)
DETECTION OF ILLEGAL CONDITIONS
Reading of undefined ROM gets zeroes The opcode for
software interrupt is zero If the program fetches instructions
from undefined ROM this will force a software interrupt
thus signalling that an illegal condition has occurred
Note A software interrupt is acted upon only when a timer or external inter-
rupt is not pending as hardware interrupts have priority over software
interrupt In addition the Global Interrupt bit is not set when a soft-
ware interrupt is being serviced thereby opening the door for the hard-
ware interrupts to occur The subroutine stack grows down for each
call and grows up for each return If the stack pointer is initialized to
2F Hex then if there are more returns than calls the stack pointer will
point to addresses 30 and 31 (which are undefined RAM) Undefined
RAM is read as all 1’s thus the program will return to address FFFF
This is a undefined ROM location and the instruction fetched will gen-
erate a software interrupt signalling an illegal condition The device
can detect the following illegal conditions
1 Executing from undefined ROM
2 Over ‘‘POP’’ing the stack by having more returns than calls
Illegal conditions may occur from coding errors ‘‘brown
out’’ voltage drops static supply noise etc When the soft-
ware interrupt occurs the user can re-initialize the stack
pointer and do a recovery procedure before restarting (this
recovery program is probably similar to RESET but might
not clear the RAM) Examination of the stack can help in
identifying the source of the error For example upon a soft-
ware interrupt if the SP e 30 31 it implies that the stack
was over ‘‘POP’’ed (with the SPe2F hex initially) If the SP
contains a legal value (less than or equal to the initialized
SP value) then the value in the PC gives a clue as to where
in the user program an attempt to access an illegal (an ad-
dress over 300 Hex) was made The opcode returned in this
case is 00 which is a software interrupt
The detection of illegal conditions is illustrated with an ex-
ample
0043
0044
0045
0046
CLRA
RC
JMP 04FF
NOP
When the device is executing this program it seemingly
‘‘locks-up’’ having executed a software interrupt To debug
this condition the user takes a look at the SP and the con-
tents of the stack The SP has a legal value and the con-
tents of the stack are 04FF The perceptive user immediate-
ly realizes that an illegal ROM location (04FF) was ac-
cessed and the opcode returned (00) was a software inter-
rupt Another way to decode this is to run a trace and follow
the sequence of steps that ended in a software interrupt
The damaging jump statement is changed
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE control register contains the
following bits
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 e 2 01 e 4 1x e 8)
IEDG
External interrupt edge polarity select
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
TRUN
Used to start and stop the timer counter
(1 e run 0 e stop)
TC1
Timer Mode Control Bit
TC2
Timer Mode Control Bit
TC3
Timer Mode Control Bit
7
0
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits
GIE
Global interrupt enable (enables interrupts)
ENI
External interrupt enable
BUSY
MICROWIRE busy shifting flag
IPND
External interrupt pending
ENTI
Timer interrupt enable
TPND
Timer interrupt pending
(timer underflow or capture edge)
C
Carry Flip flop
HC
Half carry Flip flop
7
0
HC C TPND ENTI IPND BUSY ENI GIE
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag The flag values depend upon the in-
struction For example after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved However instructions like SET C
and RESET C will set and clear both the carry flags Table V
lists out the instructions that effect the HC and the C flags
TABLE V Instructions Effecting HC and C Flags
Instr
HC Flag
C Flag
ADC
Depends on Operands Depends on Operands
SUBC Depends on Operands Depends on Operands
SETC Set
Set
RESET C Set
Set
RRC
Depends on Operands Depends on Operands
MEMORY MAP
All RAM ports and registers (except A and PC) are mapped
into data memory address space
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