COPC912C Datasheet, PDF(12/24 Page) National Semiconductor (TI)

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COPC912C Datasheet, PDF (12/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller

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Control Registers (Continued)

TABLE VI Memory Map

Address

00 to 2F

30 to 7F

80 to BF

C0 to CF

D8 to DB

DC to DF

E0 to EF

E0 to E7

F0 to FF

Contents

On-chip RAM Bytes (48 Bytes)

Unused RAM Address Space (Reads as

all ones)

Expansion Space for On-Chip EERAM

(Reads Undefined Data)

Expansion Space for I O and Registers

Port L Data Register

Port L Configuration Register

Port L Input Pins (read only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (read only)

Reserved

On-Chip Functions and Registers

Reserved for Future Parts

Reserved

MICROWIRE Shift Register

Timer Lower Byte

Timer Upper Byte

Timer Autoreload Register Lower Byte

Timer Auto reload Register Upper Byte

CNTRL Control Register

PSW Register

On-Chip RAM Mapped as Registers

(16 Bytes)

X Register

SP Register

B Register

Reading other unused memory locations will return unde-

fined data

Addressing Modes

The device has ten addressing modes six for operand ad-

dressing and four for transfer of control

OPERAND ADDRESSING MODES

This is the âânormalââ addressing mode for the chip The op-

erand is the data memory addressed by the B or X pointer

Decrement

This addressing mode is used with the LD and X instruc-

tions The operand is the data memory addressed by the B

or X pointer This is a register indirect mode that automati-

cally post increments or post decrements the B or X pointer

after executing the instruction

Direct

The instruction contains an 8-bit address field that directly

points to the data memory for the operand

Immediate

The instruction contains an 8-bit immediate field as the op-

erand

Short Immediate

This addressing mode issued with the LD B instruction

where the immediate is less than 16 The instruction con-

tains a 4-bit immediate field as the operand

Indirect

This addressing mode is used with the LAID instruction The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory

TRANSFER OF CONTROL ADDRESSING MODES

Relative

This mode is used for the JP instruction with the instruction

field being added to the program counter to produce the

next instruction address JP has a range from b31 to a32

to allow a one byte relative jump (JP a 1 is implemented by

a NOP instruction) There are no ââblocksââ or ââpagesââ when

using JP since all 15 bits of the PC are used

Absolute

This mode is used with the JMP and JSR instructions with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC) This allows jumping to any loca-

tion in the current 4k program memory segment

Absolute Long

This mode is used with the JMPL and JSRL instructions with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC) This allows jumping to any loca-

tion in the entire 32k program memory space

Indirect

This mode is used with the JID instruction The contents of

the accumulator are used as a partial address (lower 8 bits

of PC) for accessing a location in the program memory The

contents of this program memory location serves as a par-

tial address (lower 8 bits of PC) for the jump to the next

instruction

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