COPC912C Datasheet, PDF (8/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller

Functional Description (Continued)
WARNING The SIO register should only be loaded when
the SK clock is low Loading the SIO register while the SK
clock is high will result in undefined data in the SIO register
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow For safety the
BUSY flag should only be set when the input SK clock is
low
Table III summarizes the settings required to enter the Mas-
ter Slave modes of operations
The table assumes that the control flag MSEL is set
TABLE III MICROWIRE PLUS G Port Configuration
G4
G5
(SO) (SK)
G4
Config Config
Pin
Bit
Bit
G5 G6 _Operation
Pin Pin
1
1
SO
Int SK SI MICROWIRE
Master
0
1 TRI-STATE Int SK SI MICROWIRE
Master
1
0
SO Ext SK SI MICROWIRE
Slave
0
0 TRI-STATE Ext SK SI MICROWIRE
Slave
MICROWIRE PLUS MASTER MODE OPERATION
In MICROWIRE PLUS Master mode operation the SK shift
clock is generated internally The MSEL bit in the CNTRL
register must be set to allow the SK and SO functions onto
the G5 and G4 pins The G5 and G4 pins must also be
selected as outputs by setting the appropriate bits in the
Port G configuration register The MICROWIRE Master
mode always initiates all data exchanges The MSEL bit in
the CNTRL register is set to enable MICROWIRE PLUS G4
and G5 are selected as output
The user must set the BUSY flag immediately upon entering
the slave mode This will ensure that all data bits sent by the
master will be shifted in properly After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated
Note In the Slave mode the SIO register does not stop shifting even after
the busy flag goes low Since SK is an external output the SIO regis-
ter stops shifting only when SK is turned off by the master
Note Setting the BUSY flag when the input SK clock is high in the MICRO-
WIRE PLUS slave mode may cause the current SK clock for the SIO
register to be narrow When the BUSY flag is set the MICROWIRE
logic becomes active with the internal SIO shift clock enabled If SK is
high in slave mode this will cause the internal shift clock to go from
low in standby mode to high in active mode This generates a rising
edge and causes one bit to be shifted into the SIO register from the
SI input For safety the BUSY flag should only be set when the input
SK clock is low
Note The SIO register must be loaded only when the SK shift clock is low
Loading the SIO register while the SK clock is high will result in unde-
fined data in the SIO register
Timer Counter
The device has an on board 16-bit timer counter (organized
as two 8-bit registers) with an associated 16-bit autoreload
capture register (also organized as two 8-bit registers) Both
are read write registers
The timer has three modes of operation
PWM (PULSE WIDTH MODULATION) MODE
The timer counts down at the instruction cycle rate (2 ms
max) When the timer count underflows the value in the
autoreload register is copied into the timer Consequently
the timer is programmable to divide by any value from 1 to
65536 Bit 5 of the timer CNTRL register selects the timer
underflow to toggle the G3 output This allows the user to
generate a square wave output or a pulse-width-modulated
output The timer underflow can also be enabled to interrupt
the processor The timer PWM mode is shown in Figure 7
TL DD 12060 – 10
FIGURE 7 Timer in PWM Mode
TL DD 12060–8
FIGURE 6 MICROWIRE PLUS Block Diagram
MICROWIRE PLUS SLAVE MODE
In MICROWIRE PLUS Slave mode operation the SK shift
clock is generated by an external source Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G port The SK pin must be selected as an input
and the SO pin as an output by resetting and setting their
respective bits in the G port configuration register
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