COPC912C Datasheet, PDF (10/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller

Functional Description (Continued)
TIMER APPLICATION EXAMPLE
The timer has an autoreload register that allows any fre-
quency to be programmed in the timer PWM mode The
timer underflow can be programmed to toggle output bit G3
and may also be programmed to generate a timer interrupt
Consequently a fully programmable PWM output may be
easily generated
The timer counts down and when it underflows the value
from the autoreload register is copied into the timer The
CNTRL register is programmed to both toggle the G3 output
and generate a timer interrupt when the timer underflows
Following each timer interrupt the user’s program alternate-
ly loads the values of the ‘‘on’’ time and the ‘‘off’’ time into
the timer autoreload register Consequently a pulse-width-
modulated (PWM) output waveform is generated to a reso-
lution of one instruction cycle time This PWM application
example is shown in Figure 10
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FIGURE 10 Timer Based PWM Application
Interrupts
There are three interrupt sources
1 A maskable interrupt on external G0 input positive or neg-
ative edge sensitive under software control
2 A maskable interrupt on timer underflow or timer capture
3 A non-maskable software error interrupt on opcode zero
The GIE (global interrupt enable) bit enables the interrupt
function This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources This bit is
reset when interrupt is acknowledged
ENI and ENTI bits select external and timer interrupt re-
spectively Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled IEDG
selects the external interrupt edge (1 e rising edge 0 e
falling edge) The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt
IPND and TPND bits signal which interrupt is pending After
interrupt is acknowledged the user can check these two
bits to determine which interrupt is pending The user can
prioritize the interrupt and clear the pending bit that corre-
sponds to the interrupt being serviced The user can also
enable GIE at this point for nesting interrupts Two things
have to be kept in mind when using the software interrupt
The first is that executing a simple RET instruction will take
the program control back to the software interrupt instruc-
tion itself In other words the program will be stuck in an
infinite loop To avoid the infinite loop the software interrupt
service routine should end with a RETSK instruction or with
a JMP instruction The second thing to keep in mind is that
unlike the other interrupt sources the software interrupt
does not reset the GIE bit This means that the device can
be interrupted by other interrupt sources while servicing the
software interrupt
Interrupts push the PC to the stack reset the GIE bit to
disable further interrupts and branch to address 00FF The
RETI instruction will pop the stack to PC and set the GIE bit
to enable further interrupts The user should use the RETI or
the RET instruction when returning from a hardware (mask-
able) interrupt subroutine The user should use the RETSK
instruction when returning from a software interrupt subrou-
tine to avoid an infinite loop situation
The software interrupt is a special kind of non-maskable
interrupt which occurs when the INTR instruction (opcode
00 used to acknowledge interrupts) is fetched from ROM
and placed inside the instruction register This may happen
when the PC is pointing beyond the available ROM address
space or when the stack is over-popped When the software
interrupt occurs the user can re-initialize the stack pointer
and do a recovery procedure (similar to reset but not nec-
essarily containing all of the same initialization procedures)
before restarting
Hardware and Software interrupts are treated differently
The software interrupt is not gated by the GIE bit However
it has the lowest arbitration ranking Also the fact that all
interrupts vector to the same address 00FF Hex means that
a software interrupt happening at the same time as a hard-
ware interrupt will be missed
Note There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit the interrupt enable bit will be reset
but an interrupt may still occur This is because interrupt processing is
started at the same time as the interrupt bit is being reset To avoid
this scenario the user should always use a two three or four cycle
instruction to reset interrupt enable bits
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FIGURE 11 Interrupt Block Diagram
10
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