English
Language : 

COPC912C Datasheet, PDF (6/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller
Functional Description (Continued)
TL DD 12060–5
RC l 5 x POWER SUPPLY RISE TIME
FIGURE 3 Recommended Reset Circuit
OSCILLATOR CIRCUITS
The device can be driven by a clock input which can be
between DC and 5 MHz
CRYSTAL OSCILLATOR
By selecting CKO as a clock output CKI and CKO can be
connected to create a crystal controlled oscillator Table I
shows the component values required for various standard
crystal values
R C OSCILLATOR
By selecting CKI as a single pin oscillator CKI can make an
R C oscillator CKO is available as a general purpose input
and or HALT control Table II shows variation in the oscilla-
tor frequencies as functions of the component (R and C)
value
TL DD 12060–6
FIGURE 4 Clock Oscillator Configurations
TABLE I Crystal Oscillator Configuration
CKI
R1
R2
C1
C2
Freq
(kX)
(mX)
(pF)
(pF)
(MHz)
0
1
30
30 – 36
5
0
1
30
30 – 36
4
56
1
200
100 – 150
0 455
TABLE II RC Oscillator Configuration
(Part-to-Part Variation TA e 25 C)
R
C
CKI Freq
(kX)
(pF)
(MHz)
Intr
Cycle
(ms)
33
82
2 2 to 2 7
3 7 to 4 6
56
100
1 1 to 1 3
7 4 to 9
68
100
0 9 to 1 1
8 8 to 10 8
Note 3k s R s 200 kX 50 pF s C s 200 pF
HALT MODE
The device is a fully static device The device enters the
HALT mode by writing a one to the G7 bit of the G data
register Once in the HALT mode the internal circuitry does
not receive any clock signal and is therefore frozen in the
exact state it was in when halted In this mode the chip will
only draw leakage current
The device supports two different ways of exiting the HALT
mode The first method is with a low to high transition on the
CKO (G7) pin This method precludes the use of the crystal
clock configuration (since CKO is a dedicated output) and
so may be used either with an RC clock configuration (or an
external clock configuration) The second method of exiting
the HALT mode is to pull the RESET low
Note To allow clock resynchronization it is necessary to program two
NOP’s immediately after the device comes out of the HALT mode
The user must program two NOP’s following the ‘‘enter HALT mode’’
(set G7 data bit) instruction
http www national com
6