COPC912C Datasheet, PDF (5/24 Pages) National Semiconductor (TI) – COP912C/COP912CH 8-Bit Microcontroller

Pin Description
V_CC and GND are the power supply pins
CKI is the clock input This can come from an external
source a R C generated oscillator or a crystal (in conjunc-
tion with CKO) See Oscillator description
RESET is the master reset input See Reset description
PORT L is an 8-bit I O port
There are two registers associated to configure the L port a
data register and a configuration register Therefore each L
I O bit can be individually configured under software control
as shown below
Port L Config
0
0
1
1
Port L Data
0
1
0
1
PORT L
Setup
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Three data memory address locations are allocated for this
port one each for data register 00D0 configuration regis-
ter 00D1 and the input pins 00D2
PORT G is an 8-bit port with 6 I O pins (G0–G5) and 2 input
pins (G6 G7)
All eight G-pins have Schmitt Triggers on the inputs
There are two registers associated to configure the G port
a data register and a configuration register Therefore each
G port bit can be individually configured under software con-
trol as shown below
Port G
Config
0
0
1
1
Port G
Data
0
1
0
1
PORT G
Setup
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Three data memory address locations are allocated for this
port one for data register 00D4 one for configuration reg-
ister 00D5 and one for the input pins 00D6 Since G6
and G7 are Hi-Z input only pins any attempt by the user to
configure them as outputs by writing a one to the configura-
tion register will be disregarded Reading the G6 and G7
configuration bits will return zeroes Note that the chip will
be placed in the Halt mode by writing a ‘‘1’’ to the G7 data
bit
Six pins of Port G have alternate features
G0 INTR (an external interrupt)
G3 TIO (timer counter input output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input general purpose input (if clock op-
tion is R C- or external clock)
Pins G1 and G2 currently do not have any alternate func-
tions
The selection of alternate Port G functions are done through
registers PSW 00EF to enable external interrupt and
CNTRL 00EE to select TIO and MICROWIRE operations
Functional Description
The internal architecture is shown in the block diagram
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition subtraction logical or
shift operations in one cycle time There are five CPU regis-
ters
A is the 8-bit Accumulator register
PC is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register and can be auto incre-
mented or decremented
X is the 8-bit alternate address register and can be auto
incremented or decremented
SP is the 8-bit stack pointer which points to the subroutine
stack (in RAM)
B X and SP registers are mapped into the on chip RAM
The B and X registers are used to address the on chip RAM
The SP register is used to address the stack in RAM during
subroutine calls and returns The SP must be preset by soft-
ware upon initialization
MEMORY
The memory is separated into two memory spaces program
and data
PROGRAM MEMORY
Program memory consists of 768 x 8 ROM These bytes of
ROM may be instructions or constant data The memory is
addressed by the 15-bit program counter (PC) There are no
‘‘pages’’ of ROM the PC counts all 15 bits ROM can be
indirectly read by the LAlD instruction for table lookup
DATA MEMORY
The data memory address space includes on chip RAM I O
and registers Data memory is addressed directly by the in-
struction or indirectly through B X and SP registers The
device has 64 bytes of RAM Sixteen bytes of RAM are
mapped as ‘‘registers’’ these can be loaded immediately
decremented and tested Three specific registers X B and
SP are mapped into this space the other registers are avail-
able for general usage
Any bit of data memory can be directly set reset or tested
I O and registers (except A and PC) are memory mapped
therefore I O bits and register bits can be directly and indi-
vidually set reset and tested
RESET
The RESET input pin when pulled low initializes the micro-
controller Upon initialization the ports L and G are placed
in the TRl-STATE mode The PC PSW and CNTRL regis-
ters are cleared The data and configuration registers for
ports L and G are cleared The external RC network shown
in Figure 3 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes
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