COP888FH Datasheet, PDF (9/49 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply/Divide

DC Electrical Characteristics COP88xFH: (Continued)
−40˚C ≤ T_A ≤ +85˚C unless otherwise specified
Parameter
Conditions
Maximum Input Current
Room Temp
without Latchup (Notes 11, 12)
RAM Retention Voltage, V_r
500 ns Rise
and Fall Time (Min)
Input Capacitance
(Note 12)
Load Capacitance on D2
(Note 12)
Min
Typ
2
Max
±100
7
1000
Units
mA
V
pF
pF
AC Electrical Characteristics COP88xFH:
−40˚C ≤ T_A ≤ +85˚C unless otherwise specified
Parameter
Conditions
Instruction Cycle Time (t_c)
Crystal Resonator or External
R/C Oscillator
CKI Clock Duty Cycle (Note 12)
2.5V ≤ V_CC ≤ 4.0V
4.0V ≤ V_CC ≤ 5.5V
2.5V ≤ V_CC < 4.0V
4.0V ≤ V_CC ≤ 5.5V
f = Max
Rise Time (Note 12)
f = 10 MHz Ext Clock
Fall Time (Note 12)
f = 10 MHz Ext Clock
Inputs
t_SETUP
t_HOLD
Output Propagation Delay
t_PD1, t_PD0
SO, SK
All Others
MICROWIRE Setup Time (t_UWS) (Note 12)
MICROWIRE Hold Time (t_UWH) (Note 12)
MICROWIRE Output Propagation Delay (t_UPD)
Input Pulse Width (Note 13)
4.0V ≤ V_CC ≤ 5.5V
2.5V ≤ V_CC < 4.0V
4.0V ≤ V_CC ≤ 5.5V
2.5V ≤ V_CC < 4.0V
R_L = 2.2k, C_L = 100 pF
4.0V ≤ V_CC ≤ 5.5V
2.5V ≤ V_CC < 4.0V
4.0V ≤ V_CC ≤ 5.5V
2.5V ≤ V_CC < 4.0V
V_CC ≥ 4.0V
V_CC ≥ 4.0V
V_CC ≥ 4.0V
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
Min
Typ
2.5
1.0
7.5
3.0
45
200
500
60
150
Max
DC
DC
DC
DC
55
5
5
Units
µs
µs
µs
µs
%
µs
µs
ns
ns
ns
ns
0.7
µs
1.75
µs
1
µs
2.5
µs
20
ns
56
ns
220
ns
1
t_c
1
t_c
1
t_c
1
t_c
1
µs
Note 8: Maximum rate of voltage change must be less than 0.5V/ms.
Note 9: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 10: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I_DD HALT is done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V_CC;
clock monitor and comparators disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crys-
tal clock mode.
Note 11: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V_CC and the pins will have sink current
to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the
pins. This warning excludes ESD transients.
Note 12: Parameter characterized but not tested.
Note 13: t_c = Instruction cycle time.
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