COP888FH Datasheet, PDF (11/49 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply/Divide

AC Electrical Characteristics COP68xFH:
−55˚C ≤ T_A ≤ +125˚C unless otherwise specified
Parameter
Instruction Cycle Time (t_c)
Crystal Resonator or External
CKI Clock Duty Cycle (Note 19)
Rise Time (Note 19)
Fall Time (Note 19)
Inputs
t_SETUP
t_HOLD
Output Propagation Delay (Note 20)
t_PD1, t_PD0
SO, SK
All Others
MICROWIRE Setup Time (t_UWS) (Note 19)
MICROWIRE Hold Time (t_UWH) (Note 19)
MICROWIRE Output Propagation Delay (t_UPD)
Input Pulse Width (Note 20)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
Conditions
V_CC ≥ 4.5V
f = Max
f = 10 MHz Ext Clock
f = 10 MHz Ext Clock
V_CC ≥ 4.5V
V_CC ≥ 4.5V
R_L = 2.2k, C_L = 100 pF
V_CC ≥ 4.5V
V_CC ≥ 4.5V
Min
Typ
Max
Units
1.0
DC
µs
45
55
%
5
µs
5
µs
200
ns
60
ns
0.7
µs
1
µs
20
ns
56
ns
220
ns
1
t_c
1
t_c
1
t_c
1
t_c
1
µs
Note 15: Maximum rate of voltage change must be less than 0.5V/ms.
Note 16: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 17: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I_DD HALT is done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V_CC;
clock monitor and comparators disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crys-
tal clock mode.
Note 18: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V_CC and the pins will have sink current
to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the
pins. This warning excludes ESD transients.
Note 19: Parameter characterized but not tested.
Note 20: t_c = Instruction cycle time.
Comparators AC and DC Characteristics
V_CC = 5V, −40˚C ≤ T_A ≤ +85˚C
Parameter
Input Offset Voltage
Input Common Mode Voltage Range
Low Level Output Current
High Level Output Current
DC Supply Current Per Comparator
(When Enabled)
Response Time
Conditions
0.4V ≤ V_IN ≤ V_CC − 1.5V
V_OL = 0.4V
V_OH = 4.6V
100 mV
Overdrive, 100 pF Load
Min
Typ
±10
0.4
1.6
1.6
Max
±25
V_CC − 1.5
250
1
Units
mV
V
mA
mA
µA
µs
11
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