COP888FH Datasheet, PDF (18/49 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply/Divide

Timers (Continued)
DS012602-14
FIGURE 10. Timer in Input Capture Mode
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3 Timer mode control
TxC2 Timer mode control
TxC1 Timer mode control
TxC0
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxPNDB Timer Interrupt Pending Flag
TxENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Mode
1
2
3
TxC3
1
1
0
0
0
1
0
1
TxC2
0
0
0
0
1
1
1
1
TxC1
1
0
0
1
0
0
1
1
Description
PWM: TxA Toggle
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
Captures:
TxA Pos. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Interrupt A
Source
Autoreload RA
Autoreload RA
Timer
Underflow
Timer
Underflow
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Interrupt B
Source
Autoreload RB
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Pos. TxB Edge
Neg. TxB
Edge
Neg. TxB
Edge
Neg. TxB
Edge
Timer
Counts On
t_C
t_C
Pos. TxA
Edge
Pos. TxA
Edge
t_C
t_C
t_C
t_C
Power Save Modes
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the device is disabled during the HALT mode.
However, the clock monitor circuitry if enabled remains ac-
tive and will cause the WATCHDOG output pin (WDOUT) to
go low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be dis-
abled after the device comes out of reset (resetting the Clock
Monitor control bit with the first write to the WDSVR register).
In the HALT mode, the power requirements of the device are
minimal and the applied voltage (V_CC) may be decreased to
V_r (V_r = 2.0V) without altering the state of the machine.
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second
method is with a low to high transition on the CKO (G7) pin.
This method precludes the use of the crystal clock configura-
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