COP888FH Datasheet, PDF(38/49 Page) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply/Divide

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COP888FH Datasheet, PDF (38/49 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply/Divide

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Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

S/ADD REG

0000 to 006F

0070 to 007F

xx80 to xx97

xx98

xx99

xx9A

xx9B

xx9C

xx9D

xx9E to xxAF

xxB0

XXB1

xxB2

xxB3

xxB4

xxB5

xxB6

xxB7

xxB8

xxB9

xxBA

xxBB

xxBC

xxBD

xxBE

xxBF

xxC0

xxC1

xxC2

xxC3

xxC4

xxC5

xxC6

Contents

On-Chip RAM bytes (112 bytes)

Unused RAM Address Space (Reads As

All Ones)

Unused RAM Address Space (Reads

Undefined Data)

Dividend or Result Byte (MDR1)

Dividend/Multiplier or Result Byte

(MDR2)

Dividend/Result Byte or Undefined

(MDR3)

Dividend/Multiplicand or Result

Byte (MDR4)

Divisor or Multiplicand Byte (MDR5)

Multiply/Divide Control Register (MDCR)

Reserved

Timer T3 Lower Byte

Timer T3 Upper Byte

Timer T3 Autoload Register T3RA

Lower Byte

Timer T3 Autoload Register T3RA

Upper Byte

Timer T3 Autoload Register T3RB

Lower Byte

Timer T3 Autoload Register T3RB

Upper Byte

Timer T3 Control Register

Comparator Select Register (CMPSL)

UART Transmit Buffer (TBUF)

UART Receive Buffer (RBUF)

UART Control and Status Register

(ENU)

UART Receive Control and Status

UART Interrupt and Clock Source

UART Baud Register (BAUD)

UART Prescale Select Register (PSR)

Reserved for UART

Timer T2 Lower Byte

Timer T2 Upper Byte

Timer T2 Autoload Register T2RA

Lower Byte

Timer T2 Autoload Register T2RA

Upper Byte

Timer T2 Autoload Register T2RB

Lower Byte

Timer T2 Autoload Register T2RB

Upper Byte

Timer T2 Control Register

Address

S/ADD REG

xxC7

xxC8

xxC9

xxCA

xxCB

xxCC

xxCD to xxCF

xxD0

xxD1

xxD2

xxD3

xxD4

xxD5

xxD6

xxD7

xxD8

xxD9

xxDA

xxDB

xxDC

xxDD to xxDF

xxE0 to xxE5

xxE6

xxE7

xxE8

xxE9

xxEA

xxEB

xxEC

xxED

xxEE

xxEF

xxF0 to xxFB

xxFC

xxFD

xxFE

xxFF

0100 to 017F

0200 to 027F

0300 to 037F

Contents

WATCHDOG Service Register

(Reg:WDSVR)

MIWU Edge Select Register

(Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

Reserved

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Port D

Reserved for Port D

Reserved for EE Control Registers

Timer T1 Autoload Register T1RB

Lower Byte

Timer T1 Autoload Register T1RB

Upper Byte

ICNTRL Register

MICROWIRE/PLUS Shift Register

Timer T1 Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA

Lower Byte

Timer T1 Autoload Register T1RA

Upper Byte

CNTRL Control Register

PSW Register

On-Chip RAM Mapped as Registers

X Register

SP Register

B Register

S Register

On-Chip 128 RAM Bytes

Note: Reading memory locations 0070Hâ007FH (Segment 0) will return all

ones. Reading unused memory locations 0080Hâ00AFH (Segment 0) will re-

turn undefined data. Reading memory locations from other unused Segments

(i.e., Segment 4, Segment 5, â¦ etc.) will return undefined data.

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