COP888FH Datasheet, PDF (14/49 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply/Divide

Data Memory Segment RAM
Extension (Continued)
cated in the base segment. The stack pointer will be intitial-
ized to point at data memory location 006F as a result of re-
set.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.
Reset
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi-
cated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,
T2CNTRL and T3CNTRL control registers are cleared. The
USART registers PSR, ENU (except that TBMT bit is set),
ENUR and ENUI are cleared. The Comparator Select Regis-
ter is cleared. The S register is initialized to zero. The
Multi-Input Wakeup registers WKEN, WKEDG and WKPND
are cleared. (Wakeup register WKPND is unknown.) The
stack pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t_C clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t_C–32 t_C clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
*Reads as all ones.
FIGURE 5. RAM Organization
DS012602-7
RC > 5 x Power Supply Rise Time
DS012602-8
FIGURE 6. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (t_c).
Figure 7 shows the Crystal and R/C oscillator diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
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