PC87338 Datasheet, PDF (88/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

For more information, see “The Result Phase Status
Registers” on page 88.
3.4.4 Idle Phase
After a hardware or software reset, after the chip has
recovered from power-down mode or when there are
no commands in progress the controller is in the idle
phase. The controller waits for a command byte to be
written to the Data Register (FIFO). The RQM bit is
set, and the DIO bit is cleared in the MSR.
After receiving the first command (opcode) byte, the
controller enters the command phase. When the com-
mand is completed the controller again enters the idle
phase. The Digital Data Separator (DDS) remains
synchronized to the reference frequency while the
controller is idle. While in the idle phase, the controller
periodically enters the drive polling phase.
3.4.5 Drive Polling Phase
National Semiconductor’s FDC supports the polling
mode of old 8-inch drives, as a means of monitoring
any change in status for each disk drive present in the
system. This support provides backward compatibility
with software that expects it.
In the idle phase, the controller enters a drive polling
phase every 1 msec, based on a 500 Kbps data trans-
fer rate. In the drive polling phase, the controller
checks the status of each of the logical drives (bits 0
through 3 of the MSR). The internal ready line for
each drive is toggled only after a hardware or soft-
ware reset, and an interrupt is generated for drive 0.
At this point, the software must issue four SENSE IN-
TERRUPT commands to clear the status bit for each
drive, unless drive polling is disabled via the POLL bit
in the CONFIGURE command. See “Bit 4 - Disable
Drive Polling (POLL)” on page 94. The CONFIGURE
command must be issued within 500 µsec (worst
case) of the hardware or software reset to disable
drive polling.
Even if drive polling is disabled, drive stepping and
delayed power-down occur in the drive polling phase.
The controller checks the status of each drive and, if
necessary, it issues a pulse on the STEP output sig-
nal with the DIR signal at the appropriate logic level.
The controller also uses the drive polling phase to au-
tomatically trigger power down. When the specified
time that the motor may be off has expired, the con-
troller waits 512 msec, based on data transfer rates of
500 Kbps and 1 Mbps, before powering down, if this
function is enabled via the MODE command.
If a new command is issued while the FDC is in the
drive polling phase, the MSR does not indicate a
ready status for the next parameter byte until the poll-
ing sequence completes the loop. This can cause a
delay between the first and second bytes of up to 500
µsec at 250 Kbps.
3.5 THE RESULT PHASE STATUS
REGISTERS
In the result phase of a command, result bytes that
hold status information are read from the Data Regis-
ter (FIFO). These bytes are the result phase status
registers.
The result phase status registers may only be read
from the Data Register (FIFO) during the result phase
of certain commands, unlike the Main Status Register
(MSR), which is a read only register that is always val-
id.
3.5.1 Result Phase Status Register 0
(ST0)
76543210
Result Phase Status
0 0 0 0 0 0 0 0 Reset ^{Register 0 (ST0)}
Required
Logical Drive Selected
(Execution Phase)
Head Selected (Execution Phase)
Not Used
Equipment Check
SEEK End
Interrupt Code
FIGURE 54. ST0 Result Phase Register Bitmap
Bits 1,0 - Logical Drive Selected
These two binary encoded bits indicate the logical
drive selected at the end of the execution phase.
The value of these bits is reflected in bits 1,0 of the
SR3 register, described on page 91.
00 - Drive 0 selected.
01 - Drive 1 selected.
10 - If four drives are supported, or drives 2 and 0
are exchanged, drive 2 is selected.
11 - If four drives are supported, drive 3 is select-
ed.
Bit 2 - Head Selected
This bit indicates which side of the Floppy Disk
Drive (FDD) is selected. It reflects the status of the
HDSEL signal at the end of the execution phase.
The value of this bit is reflected in bit 2 of the SR3
register, described on page 91.
0 - Side 0 is selected.
1 - Side 1 is selected.
Bit 3 - Not used.
This bit is not used and is always 0.
88
www.national.com