PC87338 Datasheet, PDF (167/221 Pages) National Semiconductor (TI) – ACPI 1.0 and PC98/99 Compliant SuperI/O

DMA Swap Configuration
Logic
Module
RX -
Channel ^RX_DMA
DMA
Logic
Routing
TX -
Channel ^TX_DMA
DMA
Logic
Logic
DMA
Hand-
shake
Signals
DMASWP
FIGURE 88. DMA Control Signals Routing
5.16.3 LCR/BSR – Link Control/Bank
Select Registers
These registers are the same as in bank 0.
5.16.4 EXCR2 – Extended Control
Register 2
This register is used to configure the transmitter and
receiver FIFOs, and the baud generator prescaler.
Upon reset all bits are set to 0.
76543210
0 0 0 0 0 0 0 0 Reset
0
Required
B3–2 RF_SIZ [1–0] – RX_FIFO Levels Select.
These bits select the number of levels for the
RX_FIFO.
They are effective only when the FIFOs are en-
abled.
Bits 3–2 RX_FIFO Levels
00
16
01
32
1x
Reserved
B5–4 PRESL [1–0] – Prescaler Select.
The prescaler divides the 24 MHz input clock
frequency to provide the clock for the baud
generator.
Bits 5–4 Prescaler Value
00
13.0
01
1.625
10
Reserved
11
1.0
B6 Reserved.
Read/write 0.
B7 LOCK – Lock Bit.
When set to 1, accesses to the baud generator
divisor register through LBGD(L) and LBGD(H)
as well as fallback are disabled from non-ex-
tended mode.
In this case two scratchpad registers overlayed
with LBGD(L) and LBGD(H) are enabled, and
any attempted CPU access of the baud gener-
ator divisor register through LBGD(L) and LB-
GD(H) will access the scratchpad registers
instead. This bit must be set to 0 when extend-
ed mode is selected.
TF_SIZ0
TF_SIZ1
RF_SIZ0
RF_SIZ1
PRESL0
PRESL1
Reserved
LOCK
FIGURE 88. Extended Control Register 2
B1–0 TF_SIZ [1–0] – TX_FIFO Levels Select.
These bits select the number of levels for the
TX_FIFO.
They are effective only when the FIFOs are en-
abled.
Bits 1–0 TXFIFO Levels
00
16
01
32
1x
Reserved
167
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